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INTEGRATED CIRCUITS
DATA SHEET
SAA2502 ISO/MPEG Audio Source Decoder
Preliminary specification Supersedes data of 1997 Apr 18 File under Integrated Circuits, IC01 1997 Nov 17
Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.3 7.3.1 7.3.2 7.3.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.4.9 7.5 7.5.1 7.5.2 7.5.3 7.6 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Basic functionality Clock generator module External sample clock Free running internal sample clock Locked internal sample clock Limited sampling frequency support for internal sampling clocks Input interface module Master input mode Slave input mode Buffer controlled input mode Decoder core Frame synchronization to input data streams Master input mode bit rate generation Sample clock generation Decoder precision Scale factor CRC protection Handling of errors in the coded input data Dynamic range compression Baseband audio processing Decoder latency time Output interface module I2S output SPIDF output Bit serial analog output Control interface module Resetting Interrupts Microcontroller interface Initialization Transfer protocols Local registers APPENDIX L3 interface specification Introduction Example of a data transfer Timing requirements Timing 9 10 11 11.1 12 13 14 14.1 14.2 14.3 14.4 15 16 LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS
SAA2502
Host interface: CDATA, CCLK and CMODE APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS
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Preliminary specification
ISO/MPEG Audio Source Decoder
1 FEATURES 2 APPLICATIONS
SAA2502
* Low sampling frequency decoding possibilities (24 kHz, 22.05 kHz and 16 kHz) of MPEG2 are supported * A variety of output formats are supported: I2S, SPDIF and 256 or more times oversampled bit serial analog stereo * Automatic internal dynamic range compression algorithm using programmable compression parameters * Non byte-aligned coded input data is handled * Built-in provisions to generate high quality sampling clocks for all six supported sampling frequencies; these sampling clocks may locked to an external PLL to support an extensive list of input data reference clock frequencies * Bit-rate and sampling-rate settings may be overruled by the microcontroller while the SAA2502 is trying to establish frame synchronization * Input interface mode which requests data based on input buffer content, enables the handling of variable bit-rate input streams and input data offered in (fixed length) bursts * An interrupt output pin which can generate interrupt requests at the occurrence of various events; consequently polling by the microcontroller is not needed in most situations * L3 and the I2C-bus microcontroller interface protocols are supported * The control interface is always fully operational (also while STOP is asserted) * CRC protection of scale factors is provided for all supported sample frequencies. 4 ORDERING INFORMATION
* Astra Digital Radio (ADR) * Digital Audio Broadcast (DAB) * Digital Versatile Disc (DVD) * Digital Video Broadcast (DVB) * General purpose MPEG2 audio decoding. 3 GENERAL DESCRIPTION
The SAA2502 is a second generation ISO/MPEG audio source decoder. The device specification has been enhanced with respect to the SAA2500 and SAA2501 ICs and therefore it offers in principle all features of its predecessors. It supports layer I and II of MPEG1 and the MPEG2 requirements for a stereo decoder.
PACKAGE TYPE NUMBER NAME SAA2502H QFP44 DESCRIPTION plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm VERSION SOT307-2
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Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
5 BLOCK DIAGRAM
SAA2502
handbook, full pagewidth
MCLKIN MCLKOUT
X22OUT X22IN 27 26 PHDIF 23
VDD1 VDD3 VDD2 REFCLK 22
CDATA CMODE CCLK 8 7 9
STOP INT RESET 33 41 24 21 5
MCLK24
31 32 29 1 25 40 43
18 30 44
10 12 11
TDI TDO TCK TMS TRST SD SCK WS SPDIF
FSCLK FSCLKIN TC0 TC1
CLOCK GENERATOR
PHASE COMPARATOR
DIVIDER
DECODING CONTROL
SAA2502
3 2 4
CD CDEF CDSY CDCL CDVAL CDRQ
15 17 19 14 20 13 INPUT INTERFACE DEMULTIPLEXER DEQUANTIZATION AND SCALING SYNTHESIS SUB-BAND FILTER SPDIF ENCODER 6
39 DIGITAL-TOANALOG CONVERTER 38 34 35
LFTPOS LFTNEG RGTPOS RGTNEG
16 GND1
28 GND2
42 GND3
37
36
MGE469
REFP
REFN
Fig.1 Block diagram.
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Preliminary specification
ISO/MPEG Audio Source Decoder
6 PINNING SYMBOL FSCLK SCK SD WS TRST SPDIF CCLK CDATA CMODE INT RESET STOP CDRQ CDCL CD GND1 CDEF VDD1 CDSY CDVAL TMS REFCLK PHDIF TCK FSCLKIN X22IN X22OUT GND2 MCLK24 VDD2 MCLKOUT MCLKIN TDI RGTPOS RGTNEG REFN REFP LFTNEG LFTPOS TC0 1997 Nov 17 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DESCRIPTION sample rate clock output; buffered signal baseband audio data I2S clock output baseband audio I2S data output baseband audio data I2S word select output boundary scan test reset input SPDIF baseband audio output L3 clock/I2C-bus bit clock input L3 data/I2C-bus serial data input/output; note 1 L3 mode (address/data select input) interrupt request output; active LOW; note 1 master reset input soft reset/stop decoding input coded data request output coded data bit clock input/output; note 2 MPEG coded data input ground 1 coded data error flag input supply voltage 1 coded data byte or frame sync input coded data valid flag input boundary scan test mode select input PLL reference clock input PLL phase comparator output; note 2 boundary scan test clock input sample rate clock input 22.579 MHz clock oscillator input or signal input 22.579 MHz clock oscillator output ground 2 master clock frequency indication input supply voltage 2 master clock oscillator output master clock oscillator input or signal input boundary scan test data input analog right channel positive output analog right channel negative output low reference voltage input for analog outputs high reference voltage input for analog outputs analog left channel negative output analog left channel positive output factory test scan chain control 0 input 5
SAA2502
Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
SAA2502
SYMBOL TDO GND3 TC1 VDD3 Notes
PIN 41 42 43 44 boundary scan test data output ground 3
DESCRIPTION
factory test scan chain control 1 input supply voltage 3
1. Output type is: open-drain. 2. Output type is: 3-state.
35 RGTNEG
34 RGTPOS
38 LFTNEG
39 LFTPOS
42 GND3
36 REFN
37 REFP
44 VDD3
41 TDO
40 TC0
43 TC1
FSCLK SCK SD WS TRST SPDIF CCLK CDATA CMODE
1 2 3 4 5 6 7 8 9
33 TDI 32 MCLKIN 31 MCLKOUT 30 VDD2 29 MCLK24
SAA2502
28 GND2 27 X22OUT 26 X22IN 25 FSCLKIN 24 TCK 23 PHDIF
INT 10 RESET 11
TMS 21
REFCLK 22
STOP 12
13
CDCL 14
CD 15
GND1 16
CDEF 17
VDD1 18
CDSY 19
CDVAL 20
CDRQ
MGE468
Fig.2 Pin configuration.
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Preliminary specification
ISO/MPEG Audio Source Decoder
7 7.1 FUNCTIONAL DESCRIPTION Basic functionality 7.2 Clock generator module
SAA2502
From a functional point of view, several blocks can be distinguished in the SAA2502. A clock generator section derives the internally and externally required clock signals from its clock inputs. The input interface section receives or requests coded input data in one of the supported input interface modes. The demultiplexer processor handles frame synchronization, parsing, demultiplexing and error concealment of the input data stream The de-quantization and scaling processor performs the transformation and scaling operations on the (demultiplexed) coded sample representations in the input bitstream to yield sub-band domain samples. The sub-band samples are transferred to the synthesis sub-band filter bank processor which reconstructs the baseband audio samples. The output interface block transforms the audio samples to the output formats required by the different output ports. The decoding control block houses the microcontroller interface, and handles the response to external control signals. This section enables the application to configure the SAA2502, to read its decoding status, to read ancillary data and so on. Several pins are reserved for boundary scan test (5 pins) and factory test scan chain control (2 pins). Table 1 Clock interfacing signals DIRECTION input output input input output input output input output I2C-bus/L3
The SAA2502 clock interfacing is designed for application versatility. It consists of 9 signals (see Table 1). The clock generator provides the following clock signals: * Internal sample clocks * External buffered sample clock FSCLK * Processor master clock * Coded input data bit clock input bit rate * Coded input data request clock f = ---------------------------------32 The module can be configured to operate in 3 different modes of operation: * External sample clock mode * Free running internal sample clock mode * Locked internal sample clock mode. Clock generator operation mode must be stationary while the device is in normal operation. Changing mode should always be followed by a (soft) reset.
SIGNAL MCLKIN MCLKOUT MCLK24 X22IN X22OUT FSCLKIN FSCLK REFCLK PHDIF
FUNCTION master clock oscillator input or signal input master clock oscillator output master clock frequency indication 22.5792 MHz clock oscillator input or signal input 22.5792 MHz clock oscillator output external sample rate clock signal input sample rate clock signal output coded input data rate reference clock phase difference indication output between reference clock and sample clock
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Preliminary specification
ISO/MPEG Audio Source Decoder
7.2.1 EXTERNAL SAMPLE CLOCK Table 3
SAA2502
Internal sample clock (default mode) RESULTANT FREQUENCIES (MHz) 12.288 11.2896 8.192 6.144 5.6448 4.096 24.576 ----------------2 22.5792 -------------------2 24.576 (1) ----------------3 24.576 ----------------4 22.5792 -------------------4 24.576 ----------------6
In applications where a 256 x fs sample clock is available, the use of external crystals may be avoided by putting the SAA2502 clock generator module in `external sample clock mode'. Such mode setting may be realized by setting control flag FSCINP of the control interface. In this event the sample clock has to be provided to the FSCLKIN clock input. If sample rate switching should be supported, required clock frequency changes are the responsibility of the application. After such a clock frequency change, enforcement of a soft reset is advised. In external sample clock mode (and only in that mode) the clock generator module is able to accept a 384 x fs sample clock input. If that mode of operation is desired the control flag FSC384 should be set. The FSCLK output is normally disabled in this mode. If enabled (by setting control flag FSCENA) FSCLK will produce a buffered copy of FSCLKIN. X22IN, X22OUT, REFCLK and PHDIF are not used in this mode. X22IN and REFCLK should be connected to GND or VDD. MCLKIN is used to provide the (free running) master clock. This may either be achieved by applying a correct clock signal to MCLKIN or by connecting a crystal between MCLKIN and MCLKOUT. In external sample clock mode (and only in that mode) the master clock may deviate from 24.576 MHz. The master clock frequency value required depends on the state of pin MCLK24 (see Table 2). Table 2 Master clock frequency setting by MCLK24 FREQUENCY MCLK24 MINIMUM GND VDD 256 x fs 512 x fs MAXIMUM 12.288 MHz (256 x 48 kHz) 24.576 MHz (512 x 48 kHz)
SAMPLE FREQUENCY 256 x 48 kHz 256 x 44.1 kHz 256 x 32 kHz 256 x 24 kHz 256 x 22.05 kHz 256 x 16 kHz
Note 1. Asymmetrical FSCLK. The main advantage of this mode is that the SAA2502 determines automatically which sampling rate is active from the sampling rate setting of the input data bit stream, and then selects either MCLKIN or X22IN divided by the correct number as the sample clock source. Therefore this mode is particularly suited in applications supporting dynamically varying sampling rates. The required clocks may either be applied to MCLKIN (respectively to X22IN) or be generated by connecting a crystal between MCLKIN and MCLKOUT (respectively between X22IN and X22OUT). The recommended crystal oscillator configuration is shown in Fig.3. The specified component values only apply to crystals with a low equivalent series resistance of <40 . FSCLKIN, REFCLK and PHDIF are not used in this mode (FSCLKIN and REFCLK should be connected to VSS or VDD). MCLK24 has to be connected to VDD, while the control flags FSCINP and FSC384 should be left in their default (cleared) states. If the FSCLK output is enabled (by setting control flag FSCENA) FSCLK will produce a buffered version of 256 x fs.
7.2.2
FREE RUNNING INTERNAL SAMPLE CLOCK
This is the default mode of operation: 256 x fs for all six supported sample rates is generated internally from the clock frequencies supplied to MCLKIN (24.576 MHz) and X22IN (22.5792 MHz) as shown in Table 3.
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Preliminary specification
ISO/MPEG Audio Source Decoder
SAA2502
in such a way that SIG and 256 x fs will stem from the same source. The divisor N1 is programmable with (1 to 16) x 8 as possible values. REF on the other hand is derived from the REFCLK input. Two programmable dividers in series are used here. N2 may adopt one of 4 possible values: 5, 25, 125 or 625 while N3 can be programmed to be 1 to 32. Because both inputs of the phase comparator have to operate at identical frequencies the next equation has to be obeyed: 156.6 kHz REFCLK ------------------------- = -------------------------- or, written differently: N1 N2 x N3
handbook, halfpage C2
26 C1 X1 R1 R2 27 C3 32 C4 X2 R4 R3 31
MGE470
SAA2502
C1 = C2 = C3 = C4 = 10 pF; R1 = R4 = 100 k; R2 = R3 = 1 k; X1 = 22.5792 MHz; X2 = 24.5760 MHz.
153.6 kHz x N 2 x N 3 REFCLK = ----------------------------------------------------N1 For a list of supported REFCLK frequency values see Chapter 8. The mode of operation of the phase comparator in Fig.5 is programmable via the control flag PHSMOD:
Fig.3 Crystal oscillator components.
7.2.3
LOCKED INTERNAL SAMPLE CLOCK
This mode differs from the previous one in just a single aspect: the REFCLK and PHDIF pins are used to realize a Phase-Locked Loop (PLL) which locks the 256 x fs sample clock to the REFCLK reference clock. Because the real goal is locking sample clock and bit rate, a reference clock should be used which has a fixed relation to the input bit rate. An example of such a PLL realization is shown in Fig.4. The phase comparator output PHDIF generates a signal with a DC component proportional to the phase difference between the internal signals SIG and REF (see Fig.5). The 22.5792 MHz signal X22IN is divided by 147 and the 24.576 MHz signal MCLKIN is divided by 160. This results in the same frequency (153.6 kHz) in both events. One of the two signals is selected as input for the programmable divide by N1 unit. The selector is controlled
handbook, halfpage
LOWPASS FILTER 24.576 MHz VCXO 22.5792 MHZ VCXO
PHDIF
MCLKIN
MCLKOUT
X22IN X22OUT
SAA2502
MGE471
Fig.4 External PLL components.
handbook, full pagewidth
X22IN
DIVIDE BY 147
153.6 kHz DIVIDE BY N1 SIG
MCLKIN
DIVIDE BY 160
PHASE COMPARATOR DIVIDE BY N3 REF
PHDIF
REFCLK
DIVIDE BY N2
MGE472
Fig.5 SAA2502 phase comparator.
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Preliminary specification
ISO/MPEG Audio Source Decoder
7.2.3.1 XOR mode
SAA2502
The electrical behaviour of the PHDIF output pin in this mode is special: PHDIF is HIGH from the rising edge of REF to the rising edge of SIG and 3-stated elsewhere if REF is leading and PHDIF is low from rising edge of SIG to rising edge of REF and 3-stated elsewhere if REF is trailing. Therefore PHDIF is NOT 3-stated during a portion tup of each cycle when it acts as a pull-up device or during a portion tdown of each cycle when it acts as a pull-down device (see right part of Fig.6). As a result the locking range is always 360 degrees phase difference. The output behaviour as function of phase difference is non-symmetrical with reference to the vertical axis, but a reversed mode is also available (by setting the control flag PHSRVS).
PHDIF is the XOR function of SIG and REF. The frequency is twice the frequency of SIG and REF. The PHDIF output carries a signal, switching between GND and VDD, with an average value Vavg which is a function of the phase difference between SIG and REF (see left part of Fig.6). The locking range in this mode of operation is maximum for even values of N3 (180 degrees phase difference) but less for odd values of N3. It is minimum for N3 = 3 (120 degrees phase difference).
7.2.3.2
Edge triggered mode
PHDIF is only influenced by the rising edges of SIG and REF. Consequently its frequency is equal to the SIG and REF frequency.
handbook, full pagewidth
T
T
3-stated
PHDIF
t1 1 5/6 t2 t
XOR mode
100% tup
edge triggered mode
Vavg VDD
0%
max
1/6 tdown
min
0
0o
180o 360o REF to SIG phase difference
100%
-180o
0o +180o REF to SIG phase difference
MGE473
Fig.6 PHDIF output behaviour.
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Preliminary specification
ISO/MPEG Audio Source Decoder
7.2.4 LIMITED SAMPLING FREQUENCY SUPPORT FOR
INTERNAL SAMPLING CLOCKS
SAA2502
CDRQ changes at the falling edge of CDCL. CDVAL = logic 0 indicates that CD and CDEF should be ignored while CDVAL = logic 1 indicates that CD is a valid coded input stream data bit (CDEF is then its error attribute). CDEF = logic 0 means that the value of CD may be assumed to be reliable while CDEF = logic 1 means that the value of CD is flagged as insecure (e.g. due to erratic non-correctable channel behaviour). The value of CDEF may be different for each data bit, but is combined by the SAA2502 for every group of 8 (byte aligned) valid coded input bits. CDSY will only have effect when the SYMOD control flags are set to 10 or 11. When SYMOD = 10 the valid input bit at a rising edge of CDSY marks the start of a new byte (when SYMOD = 11 it marks the start of a new MPEG audio frame). Note that just the rising edge of CDSY is important, the falling edge has no meaning. If CDSY is used with SYMOD = 10 leading edges must be frequent enough to assure fast byte alignment, if used with SYMOD = 11 a leading edge must be present every frame. Leading edges of CDSY may occur while CDVAL is (implicitly) high. Alternatively, a situation as shown in Fig.8 is also allowed, where CDSY has a rising edge while CDVAL is low, i.e. during invalid data. The first valid CD bit after the rising edge of CDVAL is then interpreted as the first byte or frame bit. The output pin CDRQ is used to request new coded input data.
7.2.4.1
When sampling frequency is limited to 44.1 and/or 22.05 kHz:
In this event MCLKIN is only required to generate the master clock frequency. Consequently the remarks on MCLKIN frequency also apply in this special case.
7.2.4.2
When sampling frequency is limited to 48, 32, 24 and/or 16 kHz:
In this event X22IN is not required. Therefore X22IN should be connected to VSS or VDD, but it is more efficient to apply any available clock signal to X22IN. Because 44.1 kHz is the default initial sampling frequency it may also be advisable to over-rule the sampling frequency after a hard reset. 7.3 Input interface module
The input interface module handles the reception of the coded input data stream. The module can be configured to operate in 3 distinct modes of operation: * The master input mode * The slave input mode * The buffer controlled input mode. Input interface mode must be stationary while the device is in normal operation. Changing mode will result in an (automatically generated) internal soft reset. The inputs CD, CDVAL, CDEF and CDSY are all clocked at the rising edge of the CDCL bit clock. Table 4 Signals of coded data input interface DIRECTION input input input input input/output output coded data input bit
SIGNAL CD CDVAL CDEF CDSY CDCL CDRQ
FUNCTION coded data bit valid flag coded data bit error flag coded data sync (start of byte/frame) indication coded data bit clock coded data request
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Preliminary specification
ISO/MPEG Audio Source Decoder
7.3.1 MASTER INPUT MODE
SAA2502
MPEG free format bit rate is NOT allowed in this mode. Assume N is the number of CDCL periods between two transitions of CDRQ, and R is the number of CDCL periods to obtain the effective bit rate E (in kbits/s) at a CDCL 16 x 768 frequency of 768 kHz, i.e. R = ---------------------- . E The SAA2502 keeps the average value of N exactly at R, but individual values of N may vary between N = round (R) -2 and N = round (R) +2. 7.3.2 SLAVE INPUT MODE
Master input mode is the default mode of operation. This mode may also be enforced by setting the INMOD control flags to 00. Which means that the SAA2502 will generate requests for input data at regular intervals. CDVAL is not used in this mode (it should be connected to VSS or VDD). CDVAL is implicitly assumed to be logic 1 during the 2nd up to (and including) the 17th bit slot after a rising or a falling edge of CDRQ (see Fig.7). Thus signal CD should carry the coded data in bursts of 16 valid bits. In this mode the CDRQ frequency is locked to (i.e. derived from) the 256 x fs clock. Its average value equals the bit rate divided by 32. The bit clock CDCL is output, its frequency is fixed: MCLK ----------------- when MCLK24 = logic 1 32 MCLK ----------------- when MCLK24 = logic 0. 16
Slave input mode is activated by setting the INMOD control flags to 0 1. Which means that the SAA2502 will accept input data as presented by the application. In this mode it is the responsibility of the application to maintain locking between the 256 x fs sample clock and the average bit rate.
handbook, full pagewidth
CDCL
CD
,, ,,, ,, ,,,
1
2
14
15
16
,,,,,, ,, ,, ,,,, ,,
1
2
CDEF
unreliable data bit (example)
CDRQ
CDSY
start of byte or frame
valid data
valid but unreliable data
,
MGE474
invalid data
Fig.7 Master mode input data format.
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Preliminary specification
ISO/MPEG Audio Source Decoder
The bit clock CDCL is input, its frequency is determined by the application, however certain minimum and maximum values have to be obeyed. MPEG free format bit rate is allowed in this mode. CDVAL = logic 1 indicates valid data. In this way, burst input data is supported. The speed at which data may be transferred to the input interface is restricted. Transfer of an MPEG frame is illustrated in Fig.9. It shows the transfer of all Nf bits of one frame between time 0 and Tf, where Tf corresponds to 384 sample periods (MPEG layer I input data) or 1152 sample periods (MPEG layer II input data). In the figure, an example of an actual transfer characteristic is drawn. Input data may be transferred at a speed higher than bit rate (i.e. CDCL may have a frequency higher than bit rate). Ideally the data transfer of the first frame is in a single burst. In practice multiple bursts are allowed, provided that the data transfer is always within 128 CDCL cycles of the ideal data transfer.
SAA2502
Subsequent frames may also have multiple bursts, but the data transfer must always be within 128 CDCL cycles of both the first frame data transfer and the ideal single burst transfer characteristics. All frames must start within the first four bytes of a data burst. The transfer characteristic has a slope equal to CDCL frequency during the bursts (when CDVAL is high) and is horizontal outside the bursts (when CDVAL is low; no bits are transferred). The frequency of CDCL has to be constant (except when CDVAL is low) in normal operation; any change of CDCL frequency should be followed by a (soft) reset. For DAB applications there is an exception to the rule that data transfer is always within 128 CDCL cycles of the ideal single burst characteristic. When the sampling frequency is 24 kHz and the CDCL frequency is 384 kbits/s, it is allowed to send an input frame in two bursts of equal length. The first bit of a frame must be the first bit of a burst, while the last bit of a frame must be the last bit of a burst.
handbook, full pagewidth
CDCL
CD
,, ,, ,,,,,, ,, ,, ,,,,,,
unreliable data bits (example)
,, ,, ,, ,,
CDEF
CDVAL
CDSY
start of byte or frame
valid data
valid but unreliable data
,,
MGE475
invalid data
Fig.8 Slave mode input data format.
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Preliminary specification
ISO/MPEG Audio Source Decoder
SAA2502
handbook, full pagewidth
Nf (1) transferred input bits slope = maximum CDCL frequency jitter limits
MGE476
slope = CDCL frequency
slope = input bit rate (2) 0 0 Tf
time
(1) Ideal frame transfer characteristics are restricted to this area. (2) Ideal frame transfer characteristic (example).
Fig.9 Slave input data transferring speed.
The shaded area in Fig.9 represents the restrictions to the transfer characteristic of a frame. The characteristic may not cross the shown upper limit of the shaded area in order to prevent input buffer underflow and/or overflow. The slope of the upper limit is determined by the sample frequency as shown in Table 5. Table 5 Slope of the upper limit determined by sampling frequency MAXIMUM CDCL FREQUENCY (kbits/s) 768 705.6 512 384 352.8 256
SAMPLE FREQUENCY (kHz) 48 44.1 32 24 22.05 16
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Preliminary specification
ISO/MPEG Audio Source Decoder
7.3.3 BUFFER CONTROLLED INPUT MODE (see Fig.10)
SAA2502
should be delivered and so on until CDRQ is dropped. Delivery of subsequent bytes while CDRQ remains HIGH should be uninterrupted (CDVAL should stay HIGH) * There is also an option for the application to deliver part of the input data later. Despite violating the conditions in the previous paragraph, this is allowed, but with consequences for the input buffer latency time. MPEG free format bit rate is allowed in this mode. Dynamically varying bit rate may be supported in this mode. Whether such support is desired or not is indicated by the following input mode bits: * INPMOD = 10 means bit rate is assumed to be (quasi) static * INPMOD = 11 means bit rate is assumed to be dynamic.
Buffer controlled input mode is activated by setting the INMOD control flags to 1X, which means that the SAA2502 will request data based on the amount of input bytes currently residing in the input buffer. The bit clock CDCL is output, its frequency is fixed: MCLK ----------------- when MCLK24 = logic 1 32 MCLK ----------------- when MCLK24 = logic 0. 16 In this mode CDRQ = logic 1 is an indication that new input data is required. CDVAL = logic 1 indicates the delivery of valid data. The application should react to the event of an input data request as follows: * One byte of input data should be delivered within 16 CDCL cycles. If CDRQ remains high the next byte
handbook, full pagewidth
CDCL
CD
,,,,, ,, ,, ,,,,, ,, ,,
unreliable data bit (example)
,, ,, ,, ,,
CDEF
CDRQ
CDVAL
CDSY
start of byte or frame
valid data
valid but unreliable data
Fig.10 Buffer controlled mode input data format.
,, ,,
MGE477
invalid data
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Preliminary specification
ISO/MPEG Audio Source Decoder
7.4 Decoder core
SAA2502
As this pattern is slightly longer than the previous one and also contains at least one 1-to-0 transition, it may be used to obtain frame synchronization in the absence of any external alignment indication (CDSY is ignored and therefore may be left floating).
The SAA2502 fully complies with MPEG1 (layer I and II) and MPEG2 (layer I and II, L0 and R0 channels). Also some DAB specific features are supported. Free format bit rate is not supported in master input mode. Several aspects of the decoding process and audio post-processing features are offered. 7.4.1 FRAME SYNCHRONIZATION TO INPUT DATA STREAMS
7.4.1.4
General non-byte aligned mode
The SAA2502 has to localize the start of a frame before decoding may begin. The process of locating the start of a frame is called frame synchronization. There are 4 different modes of frame synchronization available. These modes are in order of decreasing speed of frame synchronization.
This mode may be entered by loading 00 into the SYMOD control flags. Frame start is detected by alternating searches for a 15-bit sync pattern 111111111111X10 (identical to the layer II mode search pattern) and a15-bit sync pattern 0111111111111X1. Because valid MPEG streams exist that do not contain the first pattern while other valid MPEG streams do not contain the second pattern a time-out counter will always be active in this mode. Time-out length is set to slightly more then 72 ms which is the length of the longest audio frame. The second pattern operates for layer I and layer II, but successful synchronization is only guaranteed when the last bit of the previous frame equals logic 0. Consequently this mode synchronizes to layer I input bit streams only if frames at least sometimes end with a logic 0 bit. Both patterns contain the 1-to-0 or 0-to-1 transition required for a reliable start-of-frame detection in the absence of external alignment information. If the SAA2502 starts at a random place in the bit stream, it may take up to one frame before a sync pattern or sync pulse is encountered. Because sync patterns may be emulated by frame content, detection of a sync is always followed by a verification period to check whether the sync is located at the start of a frame. The length of the verification period depends on the presence of CRC protection and/or a free format bit rate index. During sync search and verification the baseband audio outputs are muted. If verification fails the synchronization process is restarted.
7.4.1.1
Frame sync pulse mode
In this mode the start of each frame is marked by a rising edge of the CDSY input pin. It is the fastest and most reliable method of frame synchronization. It is activated by loading 11 into the SYMOD control flags.
7.4.1.2
Byte aligned mode
This default mode may also be enforced by loading 10 into the SYMOD control flags. The start of a frame is located by detection of the 14-bit sync pattern 111111111111X1. The probability of correct sync detection is enhanced by the fact that a rising edge of the CDSY input pin marks a location which is byte aligned with frame bounds. A rising edge of CDSY is not required at every byte edge but should occur at regular intervals for reliable frame synchronization.
7.4.1.3
Layer II non-byte aligned mode
This mode may be entered by loading 01 into the SYMOD control flags. Frame start is found by detection of the 15-bit sync pattern 111111111111X10. Table 6 Frame sync verification
LENGTH OF VERIFICATION PERIOD INPUT DATA FORMAT FREE FORMAT BIT RATE MPEG; no CRC MPEG with CRC 2 frame bit rate 1 frame NON-FREE FORMAT BIT RATE 1 frame 0 frame
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Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
7.4.2 MASTER INPUT MODE BIT RATE GENERATION
SAA2502
sample rate setting using the control interface while synchronization has not been established. The speed at which input data is requested by the input in master mode is changed in one of the following events: * When input synchronization is established at the end of the verification phase and the bit rate index of the decoded bit stream indicates a bit rate different from the one currently selected. In this event, the bit rate is adapted to the new index. * When the signal STOP is raised while the STOPRQ control flag = logic 1, input requesting is halted. Requesting resumes at the last selected input bit rate when the STOP signal is dropped. In all other events (including when the SAA2502 loses synchronization), the last selected input bit rate is maintained. Whenever the selected bit rate changes while dynamic bit rate is not enabled, the SAA2502 will generate internally a soft reset resulting in a soft mute of the output interfaces and a decoder restart in order to re-initialize internal buffer settings.
When master input mode is used, the SAA2502 fetches input data at the effective bit rate. However after a hard reset the input requests input data at the default bit rate until synchronization has been established as shown in Table 7. When the clock generator mode is `free running internal sample clock' or `locked internal sample clock' the default input bit rate is always 384 kbits/s. When the mode is `external sample clock' the SAA2502 derives the selected bit rate from the signal FSCLKIN. But initially it has no indication of the current sampling rate corresponding to FSCLKIN. Therefore the bit rate of 384 kbits/s is generated at an assumed sampling frequency of 44.1 kHz. For different sample rates, the bit rate changes proportionally. The consequence is that while the SAA2502 is synchronizing after a hard reset, the application should be able to supply input data at the given default bit rate until synchronization is established. Alternatively there is also the possibility to overrule default bit rate setting and
Table 7
Establishment of default bit rate CLOCK GENERATOR MODE FSCLKIN (kHz) don't care don't care 256 or 384 x 48 256 or 384 x 44.1 256 or 384 x 32 256 or 384 x 24 256 or 384 x 22.05 256 or 384 x 16 DEFAULT BIT RATE (kbits/s) 384 384 417.96 384 278.64 208.98 192 139.32
Free running internal clock Locked internal clock External sample clock
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Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
7.4.3 SAMPLE CLOCK GENERATION 7.4.4 DECODER PRECISION
SAA2502
When the `external sample clock' mode of the clock generator is used, the application must know the sample rate. FSCLKIN has to be applied, with a frequency which is a multiple of the sample rate. The (sample rate dependent) output interface timing signals will be generated from FSCLKIN. This mode will normally be used in applications with a fixed sample rate. Should the sample rate change, then a soft reset is strongly advised. When one of the remaining clock generator modes is used, the SAA2502 selects the active sample rate automatically, and generates the required sample rate related timing signals from its MCLKIN and X22IN clock inputs. Soft resets at sample rate changes are generated automatically. After a hard reset, a sample rate of 44.1 kHz by default is selected. Such default setting may be overruled using the control interface. SCK, WS and SPDIF will show frequency changes in any of the following 3 situations: * When the SAA2502 establishes synchronization to the coded data input bit stream at a sample rate different from the one previously selected * When the current (default) sample rate is overruled by the control interface * When the clock generator mode is changed, resulting in a switch from or to the `external sample clock mode. In all those situation the phase of WS and the data content of SPDIF will be continuous. In all other events SCK, WS and SPDIF remain operating without phase or frequency changes and the sample rate selection remains unchanged. Table 8 Effective noise level figures INTERMEDIATE ROUNDING 0.6 0.6 0.6 0.6
During decoding several multiply operations are carried out on coded samples. The results of these operations have to be rounded in order to keep the word length required for internal number representation within reasonable limits. Accumulation of these rounding errors is kept at a very low level in order to assure precise audio output samples. SAA2502 precision is specified using the output of the MPEG reference decoder based on double precision floating point calculations as a reference. Differences between that reference decoder and SAA2502 output manifest themselves as white noise. Two contributions to this noise may be identified: * Noise resulting from internal rounding on intermediate results * Noise resulting from rounding of final output samples to 16, 18, 20 or 22 bits (depending on selected output accuracy). Table 8 shows the effective noise level figures. (unit is 1 LSB of 22-bit accuracy output). Except for 22-bit accuracy, output rounding is by far the dominant effect. Consequently the SAA2502 may be considered a professional level high precision decoder.
OUTPUT ACCURACY (BITS) 22 20 18 16 Note
OUTPUT ROUNDING(1) 0.3 1.2 4.6 18.5
TOTAL NOISE LEVEL 0.7 1.3 4.7 18.5
1. The output rounding part of this precision is valid only for I2S and SPDIF outputs.
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Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
7.4.5 SCALE FACTOR CRC PROTECTION 7.4.6
SAA2502
HANDLING OF ERRORS IN THE CODED INPUT DATA
MPEG specifies an optional 16 bit CRC that may be used to verify whether an important part of each audio frame is received correctly. The following data items is protected by this CRC: * Bytes 3 and 4 of the first 4 bytes of each frame, containing most of the frame header information * Allocation information * Scale factor select information (layer II only). The scale factors are not protected by this scheme. The DAB specification includes CRC protection for scale factors. The 32 sub-bands are divided into the following 4 blocks: Block 0 = sub-bands 0 to 3 Block 1 = sub-bands 4 to 7 Block 2 = sub-bands 8 to 15 Block 3 = sub-bands 16 to 31. Each block is protected by an 8-bit CRC if that block of sub-bands is (partly) inside the current sub-band limit. The required scale factor CRCs are stored in the last bytes of the previous audio frame: * The last two bytes of each frame are reserved for ancillary data; DAB specification calls this Fixed Program Associated Data (FPAD) * Minimum 2 and maximum 4 bytes before FPAD are reserved for scale factor CRCs. The number of CRC bytes present is be derived from the sub-band limit of the following audio frame * Bytes before the CRCs are available for more ancillary data; DAB specification calls this extended Program Associated Data (XPAD), as far as not occupied by MPEG coded input data. The DAB type of scale factor CRC protection, extended to all valid sample frequency plus bit rate combinations of MPEG1 and MPEG2, and to layer I, is fully supported by the SAA2502. (DAB is restricted to MPEG1 layer II, to 48 kHz sample frequency and does not support free format bit rate). Requirements for scale factor CRC handling is indicated by the SFCRC control flag.
The SAA2502 is able to handle certain types of errors in the input data. Three error categories will be handled: * Errors flagged by the coded input data error flag CDEF * CRC failures (if MPEG and/or scale factor error protection is active) * MPEG audio frame syntax errors. Error flags in the input data will effect the decoding process if the corrupted data is inside the header, bit allocation or scale factor select information part of a frame (then the SAA2502 will `soft' mute that frame) or inside the scale factor field (then the most recent valid scale factor of the same sub-band will be copied). Error flags in other data fields will be ignored. If MPEG and/or scale factor CRCs are active the CRC result has priority over CDEF flags inside the protected fields. In applications where the MPEG CRC is always present, the protection bit (which is not CRC protected) in the MPEG header may be overruled by setting control flag CRCACT. Thus the SAA2502 is robust for data errors in the protection bit.
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Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
7.4.7 DYNAMIC RANGE COMPRESSION
SAA2502
An example showing two large step type discontinuation is shown in Fig.12. It is undesirable to apply large increasing amplification steps immediately. Consequently increasing the amplification factor is limited to the `release rate' which is also programmable: 0.0117 dB * Minimum release rate = --------------------------------384 samples (1.46 dB/s at 48 kHz; 0.488 dB/s at 16 kHz) 0.375 dB * Maximum release rate = --------------------------------384 samples (46.87 dB/s at 48 kHz; 15.625 dB/s at 16 kHz). Decreasing amplification factors, must be applied almost immediately to avoid overflow when the audio power increases rapidly; thus attack rate is non-programmable and fast.
The baseband audio output resulting from MPEG decoding has a high dynamic range (theoretically >200 dB, practically up to 120 dB for the 22-bit output mode).This feature is very attractive from the high quality audio standpoint of view, but such high dynamic range is undesirable when there is a relatively high level of background noise (e.g. for car radio). For those applications the SAA2502 offers the possibility of built in dynamic range compression: * Internal dynamic range compression is offered. Thus any standard MPEG encoded bit stream may be compressed i.e. no added compression information is required. * The dynamic range compression algorithm is fully parameterised. All major characteristics are programmable through the control interface: - Level of compression - Maximum compression - Compression offset - Compression release rate (compression attack rate has to be fixed). The dynamic range compression algorithm is based on a (in time varying) amplification factor, which is equally applied to all audio output samples. The value of the amplification factor is calculated on basis of the current audio output power level for each (sub)frame of 384 output samples. The applied power to amplification curve is shown in Fig.11. All characteristics of the curve are programmable: * Compression slope minimum = 0, maximum = 0.996 * Maximum amplification minimum = 0 dB, maximum = 23.81 dB * Offset minimum = 0 dB, maximum = 47.81 dB. Offset values close to 0 dB may result in clipped output signals. This is especially true for signals with a high amplitude-to-power ratio (an extreme example of such a signal is a maximum amplitude unit impulse). The occurrence of this effect can be avoided by selecting an offset value close to or greater than 15 dB. In the context of dynamic range compression definition, the 0 dB power reference level is defined as a sine wave shaped output signal with maximum amplitude in just one (right or left) channel. The calculation will result in an new amplification factor every 384 samples (i.e. from 8 ms at 48 kHz to 24 ms at 16 kHz sample rate). Subsequent amplification factors may vary considerably. 1997 Nov 17 20
handbook, halfpage
amplification (dB) compression slope maximum amplification
0 dB power (dB)
offset
MGE478
Fig.11 Dynamic range compression characteristic.
handbook, halfpage
MGE479
audio signal power
amplification release rate
attack rate
time
Fig.12 Amplification change rates.
Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
7.4.8 BASEBAND AUDIO PROCESSING
SAA2502
Baseband audio de-emphasis as indicated in the MPEG input data stream is performed digitally inside the SAA2502. The included `Audio Processing Unit' (APU) see Fig.19, may be used to apply programmable inter-channel crosstalk or independent channel volume control. The APU attenuation coefficients LL, LR, RL and RR may be changed dynamically by the microcontroller, writing their 8-bit indices to the SAA2502 through its control interface. The coefficient changes become effective within one sample period after writing. To avoid audible clicks at coefficient changes, the transition from the current attenuation to the next is smoothed. The relationship between the APU coefficient index and the actual coefficient (i.e. the gain) is shown in Fig.14 and in Table 9 For coefficient index 0 to 64 the step size is -316 dB and for coefficient index 64 to 255 the step size is -38 dB. The APU has no built-in overflow protection, so the application must assure that the output signals of the APU cannot exceed the 0 dB level. For an update of the APU coefficients, it may be required to increase some of the coefficients and decrease some others. The APU coefficients are always written sequentially in a fixed sequence LL, LR, RL and RR. Therefore, to prevent (temporary) internal APU data overflow, the following sequence of steps may be necessary: 1. Write LL, LR, RL and RR, but change only decreasing coefficients. Overwrite increasing coefficients with their old value (therefore do not change these yet). 2. Write LL, LR, RL and RR again, but now change increasing coefficients, keeping the other ones unchanged. Table 9 APU coefficient index and actual coefficient. APU COEFFICIENT
C - ----32
left decoded handbook, halfpage audio samples LR LL
left output audio samples
RL right decoded audio samples right output audio samples
MGB493
RR
Fig.13 Audio Processing Unit (APU).
handbook, halfpage 0
0
64
APU coefficient index
254 255
-12 (1) (2) gain (dB)
-83.25
MGE480
(1) Step -316 dB per coefficient increment. (2) Step -38 dB per coefficient increment.
APU COEFFICIENT INDEX C BINARY 00000000 to 00111111 01000000 to 11111110 11111111 DECIMAL 0 to 63
Fig.14 Relation between APU coefficient index and gain.
2 64 to 254 2 255
( C - 32 ) - ----------------------16
0
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Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
7.4.9 DECODER LATENCY TIME
SAA2502
7.4.9.1 Master and slave input interface modes
Latency time is defined as elapsed time between the moment that the first byte of an audio frame is delivered to the SAA2502 and the moment that the output response resulting from the first (sub-band) sample of the same frame reaches its maximum. Latency time results from the addition of two internal latency contributions: tlatency = tproc + tbuf. * The processing latency time (tproc) is sample frequency dependent (see Table 10). * The input buffer latency time (tbuf) is input interface mode dependent. Precision of latency time calculation is sampling rate and bit rate dependent. Maximum deviation is roughly plus or minus 4 sample periods. Table 10 Processing latency time SAMPLE FREQUENCY (kHz) 48 44.1 32 24 22.05 16 Table 11 Buffer latency time; high bit rate BIT RATE (kbits/s) 448 384 320 256 192 160 128 96 64 48 32 16 tbuf2 (ms) 5.52 6.44 7.73 9.66 12.88 15.45 19.31 25.75 38.63 51.50 77.25 154.50 tproc (ms) 6.67 7.26 10.00 13.33 14.51 20.00
Input buffer latency time tbuf = (minimum of tbuf1 and tbuf2) + cr x 3.52 ms: * tbuf1 is sample frequency dependent (see Table 10) * tbuf2 is input bit rate dependent (see Table 11 and Table 12) * cr is the ratio between maximum and actual value of MCLKIN frequency. For slave input interface mode NOT the average input bit rate should be used for table look-up, but CDCL frequency (input bit rate during the burst). For free format bit rates the table should be interpolated (tbuf2 is proportional to 1/bit rate).
tbuf1 LAYER I (ms) 8.00 8.71 12.00 16.00 17.41 24.00
tbuf1 LAYER II (ms) 24.00 26.12 36.00 48.00 52.24 72.00
Table 12 Buffer latency time; low bit rate BIT RATE (kbits/s) 416 352 288 224 176 144 112 80 56 40 24 8 tbuf2 (ms) 5.94 7.02 8.58 11.04 14.05 17.17 22.07 30.90 44.14 61.80 103.00 309.00
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Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
7.4.9.2 Buffer controlled input mode
SAA2502
Consequently the application may delay delivery of requested data until it becomes available without any effect on correct SAA2502 operation. This option constitutes delayed delivery possibility. 7.5 Output interface module
Input buffer latency time behaviour is relatively complex in this mode. At start-up (i.e. during the search-for-frame sync) latency time is very small (tbuf < 2 ms) because the input buffer remains empty. After a frame sync is detected, normal decoding starts and the buffer fills up to its desired fill level. That level will result in a buffer latency time tbuf2 (see Tables 11 and 12, tbuf1 plays no role) for constant bit rate operation. It is more complex for variable bit rates, at high bit rates the buffer will hold only a fraction of a frame, while at low bit rates it may hold many frames (each possibly of a different bit rate). Also input buffer content may deviate from the desired level because data consumption rate at the output of the buffer may be high during short periods while replenishing is limited by CDCL frequency. As a result buffer latency time in buffer controlled input mode may be predicted more or less accurately only at (re)start time. Another consequence of buffer behaviour at very low bit rates in this mode is that buffer latency time values may become large. Therefore it might be possible that the SAA2502 will request data, which is not (yet) available. In those situations the SAA2502 is requesting more data than required; storage of more than one complete frame in the input buffer is never necessary.
The output interface module produces stereo baseband output samples in three different formats at the same time: * I2S * SPDIF * 256 times oversampled bit serial analog. Any of the three outputs may be enabled or disabled in order to save dissipation and minimize EMC generation in applications that do not need all of them. Decoded mono streams and the (user) selected channel of dual channel streams are presented at both (left and right) output channels. If indicated in the coded input data, de-emphasis filtering is performed digitally on the output data, thus avoiding the need of external analog de-emphasis filter circuitry. 7.5.1 I2S OUTPUT
This output interface section generates decoded baseband audio data in I2S format (see Fig.15). The I2S output interface section consists of 3 signals (see Table 13).
handbook, full pagewidth
left sample MSB SD 1 SCK 16/18/20/22 32 LSB
right sample MSB LSB
1
16/18/20/22
32
WS
MGB502
valid data
Fig.15 I2S output serial data transfer format.
1997 Nov 17
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Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
Table 13 Signals of output interfacing SIGNAL SCK SD WS DIRECTION output output output FUNCTION data clock baseband audio data word select
SAA2502
7.5.2.2 Frame synchronization patterns (Bits 0 to 3, SPDIF subframe)
The frame synchronization patterns are based on bi-phase violations. They are sent as shown in Table 14 The sequences are sent in place of 4 bi-phase coded bits 0 to 3. They are not bi-phase coded, but are sent as they are. Table 14 Frame synchronization patterns BINARY 11101000 PATTERN B DESCRIPTION left sub-frame follows. SPDIF super-frame starts. Bit 0 of left C channel will be sent in this subframe right subframe follows left subframe follows
The frequency of clock SCK is 64 times the sample frequency. The signal SD is the serial baseband audio data, sample by sample (left/right interleaved; the left sample and the right immediately following it form one stereo pair). 32 bits are transferred per sample per channel. The samples are transmitted in two's complement, MSB first. The output samples are rounded to either 16, 18, 20 or 22 bit precision, selectable by the control interface flags RND1 and RND0. The remainder of the 32 transferred bits per sample per channel are zero. The word select signal WS indicates the channel of the output samples (LOW if left, HIGH if right). 7.5.2 SPIDF OUTPUT
11100100 11100010
W M
7.5.2.3
Validity flag (bit 28, SPDIF subframe, V bit)
7.5.2.1
SPIDF format
The SPDIF data format is frame based. One SPDIF frame represents one audio sampling period. Complete frames must be transmitted at the audio sample rate. Every frame comprises two sub-frames, each of 32 bits. The data is transmitted in bi-phase mark modulated format to ensure a zero DC component. Four bits of data at the beginning of each sub-frame are assigned to frame and sub-frame synchronization, which is achieved using a set of 3 output sequences which violate the bi-phase mark rules. The audio samples occupy 24 bits (bits 4 to 27), transmitted LSB first. Depending on the selected accuracy the 2, 4, 6 or 8 LSBs will be logic 0. Bits 28 to 31 are occupied by the validity flag for the audio sample, a channel status bit (each super-frame of 192 frames contains two groups of 192 channel status bits, one for each channel), a user data bit, and a parity bit (even parity for bits 4 to 31). These bits are described respectively as V, U, C and P in the SPDIF specification. The synchronization for the channel status frame is achieved by a pair of preamble violation sequences. The synchronization for the user channel data is embedded within the data.
The V bit is intended to indicate an invalid data sample. Equipment connected to the interface is expected to perform interpolations across small numbers of invalid (V = logic 1) samples. Owing to the manner in which data is decoded in the SAA2502, and the sub-band processing of the signal, an input data error affects output audio signals in a complex way. There is not a simple relationship between input errors and damaged audio samples. Therefore the validity flag value is made programmable (through the control interface unit) Control software can use this bit in any way required.
7.5.2.4
User channel data (bit 29, SPDIF subframe, U bit)
There is a single user data channel. Two bits of data in this channel are transmitted in each frame. For this minimum implementation only the possibility to send single byte user messages to the user channel is offered. Each byte sent will be preceded by a single logic 1 valued start bit. The 8 bits of the user message are then sent LSB first.
7.5.2.5
Channel status data (bit 30, SPDIF sub-frame, C bit)
A group of C channel status bits consists of 192 bits. Two groups of channel status bits are transmitted every super-frame (one group for each channel) at a rate of one bit per sub-frame. In this application, both channel status words will be identical.
1997 Nov 17
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Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
Table 15 Channel status data DESCRIPTION Control field; note 1 0 1 2 3 and 4 5 6 and 7 Category code Source number Channel number Sample frequency; note 2 8 to 15 16 to 19 20 to 23 24 to 27 BITS 0 0 C 00 0 00 00000000 0000 0000 0100 = 48 kHz 0000 = 44.1 kHz 1100 = 32 kHz Clock accuracy; note 3 28 and 29 FIELD INDICATION indicates consumer use
SAA2502
logic 1 reserved for digital data and further standardization logic 0 = copy prohibited; logic 1 = copy permitted no pre-emphasis (SAA2502 has automatic de-emphasis) 2 channel audio data mode 0 indication 2 channel don't care don't care
field filled in accordance with clause 4.2.2.2 of the SPDIF standard:
field filled in accordance with clause 4.2.2.2 of the SPDIF standard: 00= level II (normal accuracy of 0.1%)
Notes 1. This field is filled according to clause 4.2.2.2 of the SPDIF standard `Channel status data format for digital audio equipment for consumer use' (mode 0). 2. The low sample frequencies of MPEG2 are not defined yet. In order to be able to follow future standardization, the code sent for the three remaining sampling frequencies (24, 22.05 and 16 kHz) is programmable through the controller interface. 3. The remaining 162 bits of each channel status word will all be logic 0. Individual bits of the status channel will be sent bit 0 first.
7.5.2.6
Parity (bit 31, SPDIF sub-frame, P bit)
Table 16 SPDIF interface control BIT/BYTE V bit C bit U byte DEFAULT default = logic 0 default = logic 1 uuuuuuuu RESULT valid audio data digital copy permitted 8 bits user byte
Even parity is generated on the 28 sub-frame data bits (4 to 31) in bit 31.
7.5.2.7
SPDIF control
The SPDIF interface will be controlled by the microcontroller via the control interface. The V bit is copied into each SPDIF subframe (once for each data sample). The C bit is inserted twice per SPDIF super-frame into the channel status data (bit 2 in each C channel). The user byte is inserted into the user channel (preceded by a start bit) immediately after reception through the control interface, otherwise the user channel is filled with logic 0s.
7.5.2.8
Channel status
The sampling frequency bits (bits 24 to 27) are derived from the sampling frequency index bits of the input data stream
7.5.2.9
User data
Only single 8 bit messages are sent. Individual messages should be time separated far enough to insert at least 9 logic 0s in between (for easy synchronization at the receiver end at random entry points in the stream). 1997 Nov 17 25
Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
7.5.3 BIT SERIAL ANALOG OUTPUT
SAA2502
The two analog outputs deliver a `pulse density modulated' signal, switching between REFN and REFP. The format is programmable (through the control interface): * Non return-to-zero format (subsequent logic 1 pulses are merged) * Return-to-zero format (subsequent logic 1 pulses are separated by logic 0 levels). The quality of the analog output signal depends on several external factors: * Stability and decoupling of the analog supply * Absence of jitter on the sample clock * Which external low-pass filter circuit is used * The layout of the low-pass filter. The recommended external low-pass filter is shown in Fig.17. With this circuit the DACs performance is <-75 dB (THD + N)/S with a 1 kHz sine wave, measured over the bandwidth 20 Hz to 20 kHz. The amplifier in the low-pass filter circuit is the Class AB stereo headphone driver TDA1308. The recommended DAC output format is non return-to-zero, this has a better signal-to-noise ratio than the return-to-zero format.
In order to serve applications which require low to medium performance stereo audio output, two bit serial analog outputs are provided (one for each channel). The on-chip DACs each consist of three functional blocks in series: * 4 x fs up-sampling filter * AC and DC dithering block * N x fs noise shaper; see Table 17. Table 17 Value of N for N x fs noise shaper MODE External sample clock mode SAMPLE RATE FSC384 = 0 FSC384 = 1 Other clock generator modes fs = 48 kHz fs = 44.1 kHz fs = 32 kHz fs = 24 kHz fs = 16 kHz VALUES N = 256 N = 384 N = 256 N = 256 N = 384 N = 512 N = 768
fs = 22.05 kHz N = 512
handbook, full pagewidth
LFTPOS RGTPOS 0 1 1 0 0 1 bit serial data LFTNEG RGTNEG 0 1 1 0 0 1
non-return-to-zero (recommended)
return-to-zero
MGE481
Fig.16 Bit serial output formats.
1997 Nov 17
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Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
SAA2502
handbook, full pagewidth
220 pF
neg
10 k
10 k 390 pF
11 k 100 F output
SAA2502H
pos 10 k
10 k 220 pF
TDA1308T
11 k +2.5 V
10 k
MBH974
Fig.17 External low-pass filters
7.6 7.6.1
Control interface module RESETTING
considered to be unreliable (as if CDEF were asserted). Consequently frame synchronization and decoding will not resume until STOP is de-asserted. The hard reset signal RESET has the same effect as STOP but it will also force the control interface settings into their default states. RESET must stay high during at least 24 MCLKIN periods if MCLK24 = logic 1 or 12 MCLKIN periods if MCLK24 = logic 0. 7.6.2 INTERRUPTS
Table 18 Resetting is performed by 2 signals SIGNAL STOP RESET DIRECTION input input FUNCTION soft reset and stop decoding hard reset: force default settings
A rising edge of the signal STOP triggers the next event. The decoding process is interrupted and the input buffer is flushed. Consequently audio frame synchronization is abandoned and the decoder starts searching for a new sync in the coded input data stream. In the meantime the output interface is soft muted (i.e. the output signal fades away in approximately 500 samples). There are several other events that have the same effect as a rising edge of the STOP signal: * Change of the current MPEG layer in the input stream * Change of the current sampling frequency in the input stream * Change of the current bit rate in the input stream (variable bit rate is NOT supported) * Change of current input interface mode (INMOD1 and 0) and/or audio frame synchronization mode (SYMOD1 and 0) setting * Enforcement of a soft reset through the control interface. There is also a level triggered effect which remains provided STOP is asserted. When the STOPRQ control flag is set input data requesting will be halted, otherwise normal input interface behaviour will continue at the bit rate that was valid before STOP assertion but all data is 1997 Nov 17 27
The SAA2502 is able to generate an interrupt upon the occurrence of one or more of the following events: * Status bit DST0 has been set (i.e. ancillary/PAD data, frame headers and error report are available) * Rising edge of STOP input signal * MPEG CRC check failed * Status bit INSYNC has been set * Status bit INSYNC has been cleared. For more information on these items see Sections 7.6.6.1 and 7.6.6.9. Each of these interrupts sources may be enabled or disabled as required by the application. After a hard reset all interrupt sources are disabled. When the host processor is interrupted by the SAA2502 it should read the interrupt event register to find out which event or events caused the interrupt. Reading this register will also clear all pending interrupts. The interrupt pin is active LOW (INT = logic 0 indicates an interrupt) and it is of the `open drain' type. Consequently it is allowed to `wire OR' this pin with interrupt pins of the same type of other devices. For correct operation an external pull-up resistor should be provided.
Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
7.6.3 MICROCONTROLLER INTERFACE
SAA2502
The microcontroller interface operates in one of two distinct modes of operation: L3 or I2C-bus. Mode setting is determined at initialization. The interface uses 3 signals. The function of these signals in the two modes is indicated in Table 19: Typical advantages of the use of the L3 protocol are: * High speed protocol (normally the speed of the microcontroller will be the limiting factor) * The protocol may be implemented using microcontrollers featuring only standard I/O ports. The implemented I2C-bus interface is of the 400 kbits/s, 7-bit address, EMC improved type. Typical advantages of the use of the I2C-bus protocol are: * Standardized protocol which is implemented in hardware in many existing microcontrollers * Good robustness against external disturbances on interconnecting lines * May be applied in multi-master configurations. The CDATA output driver is of the `open drain' type in order to be compliant with the I2C-bus specification. During a hard reset of the device, the microcontroller interface mode is determined. As a consequence, the interface cannot be used while the RESET signal is asserted. Table 19 Bus modes SIGNAL CDATA CCLK CMODE 7.6.4 L3 MODE L3DATA L3CLK L3MODE I2C-BUS MODE SDA SCK none DIRECTION input/output input input DESCRIPTION microcontroller interface serial data microcontroller interface bit clock microcontroller interface mode select
INITIALIZATION
Mandatory actions that must be taken for correct microcontroller interface start-up at a hard reset (see Fig.18).
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Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
SAA2502
handbook, full pagewidth
RESET
I2C-bus mode CMODE
CCLK
(1) (2)
,,,, ,,,,
(3)
L3 mode
MGE482
(1) The value of the CMODE signal while RESET is asserted defines the microcontroller interface mode; CMODE = logic 1 = I2C-bus, CMODE = logic 0 = L3. No transfers can be performed (CCLK stays HIGH). (2) L3 mode of operation only. For a correct initialization of the interface unit, it is mandatory to make CMODE HIGH and LOW again after RESET has been de-asserted. This must occur before any L3 transfer (even to or from other devices) is performed. As shown CCLK should stay HIGH during this step. (3) Now the first transfer can be performed on the microcontroller bus. Any deviation from these steps may result in undefined behaviour of the microcontroller interface, even with the possibility of disturbing transfers to other devices connected to the control bus. At a hard reset, all writeable data items are forced to their default values.
Fig.18 Microcontroller interface initialization procedure.
7.6.5
TRANSFER PROTOCOLS
7.6.5.1
L3 transfer protocol
The protocol enables writing of settings and reading of status and/or data. In this protocol, the host first issues a 6-bit wide `device address' on CDATA while CMODE = logic 0. All devices connected to the bus read this address. Then data transfers to or from the host are carried out while CMODE = logic 1. All devices with a different device address must neglect these data transfers until the next address is issued. Only the device with an address equal to the issued device address performs the transfer. Table 20 L3 device address. BIT 7 0 Note 1. The `Data Operation Mode' bits DOM1 and DOM0 define the current sub-mode of the control interface until the next time a device address is issued (see Table 21). Table 21 DOM1 and DOM0 bits DOM1 0 0 1 1 DOM0 0 1 0 1 FUNCTION data (new local register contents) sent to the SAA2502 data (current local register contents) sent to the microcontroller local register address sent to the SAA2502 short (1 byte) SAA2502 status report sent to the microcontroller BIT 6 1 BIT 5 1 BIT 4 0 BIT 3 0 BIT 2 0 BIT 1 DOM1(1) BIT 0 DOM0(1)
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SAA2502
handbook, full pagewidth READ
status
(2) 1 1 (1) (4) H status to microcontroller H (1)
(1)
H
SAA2502 address
READ (block) data
(1) (2) (1) (3) (1) H
H
SAA2502 address
1
0
H
local register address
(1)
(1) H local register data to microcontroller H
SAA2502 address (2)
0
1
(4)
WRITE (block) data
(1) (2) (1) (3) local register address (1) H
H
SAA2502 address
1
0
H
(1)
(1) H microcontroller data to local register H
SAA2502 address (2)
0
1
(3)
MGE483
(1) Halt mode. (2) Addressing mode. (3) Data from microcontroller to SAA2502. (4) Data from SAA2502 to microcontroller.
Fig.19 L3 transfer protocol.
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ISO/MPEG Audio Source Decoder
7.6.5.2 I2C-bus transfer protocol (see Fig.20)
SAA2502
The protocol enables reading of data and writing of settings. In this protocol, the host first issues a 7-bit wide `device address' on CDATA immediately after the generation of a START condition. All devices connected to the bus read this address. Data transfers to or from the host are then carried out. All devices with a different device address must neglect these data transfers until the next address is issued. Only the device with an address equal to the issued device address performs the transfer. Table 22 I2C-bus device address BIT 7 0 Notes 1. R/W determines the direction of the subsequent data transfer(s): logic 0 = write, data is sent to the SAA2502; logic 0 = read, data is sent to the microcontroller. 2. For further description of the acknowledge bit ACK consult the I2C-bus specification. BIT 6 0 BIT 5 1 BIT 4 1 BIT 3 1 BIT 2 0 BIT 1 1 BIT 0 R/W(1) - ACK(2)
READ (block) handbook, full pagewidth
(1)
data
(2) 0 (4) (3) (4)
S
SAA2502 address
0
local register address
0
(1)
(4)
(3)
S
SAA2502 address
1
0
local register data to microcontroller (4)
0 (3)
(3)
(2) P
local register data to microcontroller
1
WRITE (block) data
(1) (4)
(4) (4)
(3)
S
SAA2502 address
0
0
local register address
0 (4)
(3)
(2)
microcontroller data to local register (3)
0
P
MGE484
(1) START condition. (2) STOP condition. (3) Transfer from microcontroller to SAA2502. (4) Transfer from SAA2502 to microcontroller.
Fig.20 I2C-bus transfer protocol.
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ISO/MPEG Audio Source Decoder
Data is transferred to or from the SAA2502 in local register units (1 byte). Local registers may be of readable and/or of writeable type. A local register transfer is initiated by writing the corresponding local register address. The local register unit content is then transferred.
SAA2502
Several individual registers store more than one byte of data. To program them, transmit their local address, followed by all the data bytes, in sequence.
7.6.5.4
Restricted type registers
7.6.5.3
Register block type
Some sets of local registers are organized in blocks. One local register address is assigned to a complete block. The local register block address points to the first local register of the block. Blocks may be accessed only sequentially by reading or writing successively to the individual members of the block. Reading or writing a restricted type block may be interrupted if desired by stopping at any location in the block. Transferring may then continue later via a new block operation using a special local address (provided that no other restricted type local SAA2502 address has been sent since). This special address is labelled `continue block' (see Section 7.6.6.11). The set of four APU registers is a special type that has an auto increment option. The local addresses of these registers are adjacent to each other. To save time there is an option to programme them in sequence, in one I2C-bus transmission. After an initial local address (14H to 17H) the data for each APU coefficient follows in sequence, without the need for transmitting other local addresses. The auto increment will (if required) scroll round from the last local address (17H) back to the first local address (14H). Only the APU registers have local addresses that provide the auto increment option.
Some local registers and/or local register blocks are of the so-called `restricted type'. Access of such registers is subject to the following limitations: * Transfer speed in L3 mode is limited to 800 kbits/s. There are no special speed limitations in I2C-bus mode other than the 400 kbits/s specification limit. Both maximum speeds are scaled down proportionally when the MCLK24 frequency is below maximum. * Restricted registers should not be accessed more frequently than once per audio frame. Section 7.6.6 describes the category of each local register/block. 7.6.6 LOCAL REGISTERS
7.6.6.1
Status
The host may check the SAA2502 status by reading the one byte status word. Reading status may be accomplished in two ways: * Using the special read status protocol of the L3 mode * Using the normal data exchange protocol. The status byte read branch of the protocol may be looped an arbitrary number of times. If read is looped, status is updated between individual readings. The status bits are shown in Table 23.
Table 23 Status register: status is 1 byte (read-only, unrestricted type, local address = 1AH) BIT 7 DST1 BIT 6 DST1 BIT 5 undefined BIT 4 undefined BIT 3 undefined BIT 2 undefined BIT 1 INSYNC BIT 0 undefined
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ISO/MPEG Audio Source Decoder
Table 24 Explanation of bits in Table 23 BIT DST1 and DST0 DESCRIPTION
SAA2502
By interpreting DST1 and 0, the host can synchronize to the input frame frequency and also determine at which moment specific data items are available to be read. The value of DST1 and 0 is only valid if flag INSYNC is set. This is a modulo 2 frame counter, i.e. DST1 inverts at the moment the decoding of a new frame is started. DST1 enables the host to sample the data items available flag DST0 less frequently, meanwhile enabling the host to see if it missed a state. Bit indicates whether data items are available to be read; note 1: logic 0 indicates updating of data items is in progress (consequently they are invalid) logic 1 indicates ancillary (or PAD) data, frame headers and error report are valid.
DST1
DST0
INSYNC
Synchronization indication: logic 0 indicates not synchronized to input audio frame borders logic 1 indicates synchronized to input audio frame borders; note 2.
Notes 1. DST0 values in general do not have a determined duration. However, DST0 = logic 1 lasts at least 0.4 frame period when MPEG layer I data is decoded, and 0.8 frame period when MPEG layer II data is decoded. Table 25 indicates the validity of the SAA2502 readable data items with respect to the decoding subprocess. 2. Some of the readable local register bits only have significance if INSYNC is logic 1. Table 25 Validity of the SAA2502 readable data items with respect to the decoding subprocess DECODING FRAME n DST1 = 0 DST0 = 0 Not valid; note 1 DST0 = 1 ancillary data (frame n - 1) frame headers (frame n) error report (frame n) Note 1. Reading of a data item in a period when it is not valid renders undefined data DST0 = 0 not valid; note 1 DECODING FRAME n + 1 DST1 = 1 DST0 = 1 ancillary data (frame n) frame headers (frame n + 1) error report (frame n+1)
7.6.6.2
Clock generator control
Table 26 Clock generator control 1: 1 byte (write-only, unrestricted type, local address = 11H) BIT 7 FSCINP BIT 6 FSC384 BIT 5 FSCENA BIT 4 N3b4 BIT 3 N3b3 BIT 2 N3b2 BIT 1 N3b1 BIT 0 N3b0
Table 27 Clock generator control 2: 1 byte (write-only, unrestricted type, local address = 12H) BIT 7 N2b1 BIT 6 N2b0 BIT 5 N1b3 BIT 4 N1b2 BIT 3 N1b1 BIT 2 N1b0 BIT 1 PHSRVS BIT 0 PHSMOD
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ISO/MPEG Audio Source Decoder
Table 28 Explanation of bits in Tables 26 and 27 BIT FSCINP external sample clock mode: DESCRIPTION
SAA2502
logic 0(1): internal sample clock mode (sample clock derived from MCLKIN and X22IN clock inputs) logic 1: external sample clock mode (FSCLKIN is sample clock input) FSC384 external sample clock frequency indication: logic 0(1): FSCLKIN is 256 x fs logic 1: FSCLKIN is 384 x fs FSCENA FSCLK output enable flag: logic 0(1): FSCLK output is disabled logic 1: FSCLK output is enabled PHSMOD phase detector mode of operation: logic 0(1): edge triggered mode of operation logic 1: XOR mode of operation PHSRVS reversed phase detection: logic 0(1): normal phase detection logic 1: reversed phase detection (characteristics mirrored with reference to vertical axis) N1b3 to 0 N2b1 to 0 N3b4 to 0 Note 1. Default settings (settings value after a hard reset). code for N1 value: `0'(1) N1 = 8; `1' N1 = 16; `2' N1 = 24; `3' N1 = 32; `4' N1 = 40; `5' N1 = 48; `6' N1 = 56; `7' N1 = 64 code for N2 value: `0'(1) N2 = 5; `1' N2 = 25; `2' N2 = 125; `3' N2 = 625 N3 - 1; range 0(1) to 31 (N3 is 1 to 32)
7.6.6.3
Input and decoding control
Table 29 Input and decoding control: 1 byte (write-only, restricted type, local address = 33H) BIT 7 SYMOD1 BIT 6 SYMOD0 BIT 5 INMOD1 BIT 4 INMOD0 BIT 3 STOPRQ BIT 2 CRCACT BIT 1 SELCH2 BIT 0 SFCRC
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ISO/MPEG Audio Source Decoder
Table 30 Explanation of bits in Table 29 BIT SYMOD1 and SYMOD0 audio frame synchronization mode: 00(1): general non-byte aligned frame synchronization 01: MPEG layer II non-byte aligned frame synchronization 10: byte aligned frame synchronization 11: sync pulse frame synchronization INMOD1 and INMOD0 input interface mode of operation: 00(1): master input mode for static bit rates 01: slave input mode for static bit rates 10: buffer controlled input mode for static bit rates 11: buffer controlled input mode for variable bit rates STOPRQ enable stop requesting flag: 0(1): input requesting continues when STOP = logic 1 1: input requesting stops when STOP = logic 1 CRCACT CRC presence: DESCRIPTION
SAA2502
0(1): protection bit in the MPEG frame header is used to determine CRC presence 1: CRC is assumed be present by definition (the protection bit is overruled) SELCH2(2) dual channel mode channel select (with other modes of input data = don't care): 0(1): select channel I 1: select channel II SFCRC enable scale factor CRC protection: 0(1): no scale factor protection 1: scale factor CRC protection enabled Notes 1. Default settings (settings value after a hard reset). 2. The SAA2502 can only decode one of the dual channels, at a time. Both left and right audio outputs then play the selected channel. Table 31 Sampling rate and bit rate: 1 byte (write-only, unrestricted type, local address = 1BH) BIT 7 SFX2 BIT 6 SFX1 BIT 5 SFX0 BIT 4 BRX4 BIT 3 BRX3 BIT 2 BRX2 BIT 1 BRX1 BIT 0 BRX0
Table 32 Soft reset: 1 byte (write-only, unrestricted type, local address = 1EH) BIT 7 0 BIT 6 0 BIT 5 0 BIT 4 0 BIT 3 0 BIT 2 0 BIT 1 0 BIT 0 0
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Table 33 Sample frequency index setting SFX2 to SFX0(1) 000 001 010 011 100 101 110 111 Notes 1. Modification of SFX values is only possible while INSYNC = logic 0. Writing the sample rate control word while INSYNC = logic 1 will have no effect. 2. Default settings (settings value after a hard reset). SAMPLE FREQUENCY (kHz) 22.05 24 16 - 44.1(2) 48 32 - Table 34 Input bit rate index setting BRX4 to BRX0(1) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Notes - 8 16 24 32 40 48 56 - 16 32 48 64 80 96 112 128 144 160 176 192 - 224 - 256 288 320 352 384(2) 416 448 -
SAA2502
BIT RATE (kbits/s)
1. Modification of BRX values is only possible while INSYNC = logic 0. Writing the bit rate control word while INSYNC = logic 1 will have no effect. 2. Default settings (settings value after a hard reset).
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ISO/MPEG Audio Source Decoder
7.6.6.4 Soft reset
SAA2502
Writing to this local address has the same effect as a rising edge at the STOP input (pin 12).
7.6.6.5
Dynamic range compression control
Table 35 DRC control registers: 4 bytes (read/write, restricted block type, local address = 20H) SUBSEQUENT BYTES Compression slope Maximum compression Compression offset Release rate 7 CSLP7 0 COFS7 0 6 CSLP6 CMAX6 COFS6 0 5 CSLP5 CMAX5 COFS5 0 4 CSLP4 CMAX4 COFS4 CRRT4 3 CSLP3 CMAX3 COFS3 CRRT3 2 CSLP2 CMAX2 COFS2 CRRT2 1 CSLP1 CMAX1 COFS1 CRRT1 0 CSLP0 CMAX0 COFS0 CRRT0
Table 36 Explanation of bits in Table 35 BIT CSLP7 to CSLP0 CMAX6 to CMAX0 COFS7 to COFS0 CRRT4 to CRRT0 compression slope range 0(1) to 255; unit = 1256 dB per dB maximum amplification range 0(1) to 127; unit = 316 dB compression offset range 0(1) to 255; unit = 316 dB release rate range 1(1) to 31; unit = 3256 dB per 384 samples Note 1. Default settings (settings value after a hard reset). DESCRIPTION
7.6.6.6
Output control
The output interface is controlled by 4 local registers and a register block. Table 37 Output control register: 1 byte (write-only, unrestricted type, local address = 10H) BIT 7 SPDENA BIT 6 I2SENA BIT 5 ANAENA BIT 4 ANARTZ BIT 3 RND1 BIT 2 RND0 BIT 1 SPD_V BIT 0 SPD_C
Table 38 SPDIF sf code 1: 1 byte (write-only, unrestricted type, local address = 18H) BIT 7 22C3 BIT 6 22C2 BIT 5 22C1 BIT 4 22C0 BIT 3 24C3 BIT 2 24C2 BIT 1 24C1 BIT 0 24C0
Table 39 SPDIF sf code 2: 1 byte (write-only, unrestricted type, local address = 19H) BIT 7 0 BIT 6 0 BIT 5 0 BIT 4 0 BIT 3 16C3 BIT 2 16C2 BIT 1 16C1 BIT 0 16C0
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ISO/MPEG Audio Source Decoder
Table 40 SPDIF user byte: 1 byte (write-only, unrestricted type, local address = 1FH) BIT 7 SPDU7 BIT 6 SPDU7 BIT 5 SPDU5 BIT 4 SPDU4 BIT 3 SPDU3 BIT 2 SPDU2 BIT 1 SPDU1
SAA2502
BIT 0 SPDU0
Table 41 Explanation of bits in Tables 37, 38, 39 and 40 BIT SPDENA enable SPDIF output pin: logic 0(1): SPDIF output pin is disabled logic 1: SPDIF output pin is enabled I2SENA enable I2S output: logic 0(1): I2S output is disabled logic 1: I2S output is enabled ANAENA enable analog output: logic 0: analog output is disabled logic 1(1): analog output is enabled ANARTZ analog output return-to-zero mode: logic 0(1): non return-to-zero mode; subsequent logic 1's in analog outputs are merged logic 1(2): return-to-zero mode; subsequent logic 1's in analog outputs are separated RND1 and 0 I2S and SPDIF output sample rounding control: 00(1): output rounded to 16 bits 01: output rounded to 18 bits 10: output rounded to 20 bits 11: output rounded to 22 bits SPD_V value of validity flag (V bit) in SPDIF output format: logic 0(1): valid logic 1: not valid SPD_C value of copy permission flag (C bit) in SPDIF output format: logic 0(1): copy prohibited logic 1: copy permitted 22C3 to 22C0 24C3 to 24C0 16C3 to 16C0 SPDU7 to SPDU0 Notes 1. Default settings (settings value after a hard reset). 2. ANARTZ = logic 1 is only allowed in internal sample clock mode; FSCINP = logic 0 in clock generator control word 1. APU coefficients are set by writing their 8-bit indices to the 4-byte APU coefficient local register block. At a hard reset, indices LL and RR are set to 0 (no attenuation) and indices LR and RL to 255 (infinite attenuation; no crosstalk). SPDIF code used for 22.05 kHz sample frequency; default = 0100(1) SPDIF code used for 24 kHz sample frequency; default = 0110(1) SPDIF code used for 16 kHz sample frequency; default = 0111(1) SPDIF user byte (content of byte is sent on SPDIF user channel); default = inactive(1) DESCRIPTION
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ISO/MPEG Audio Source Decoder
Table 42 APU coefficients: 4 bytes (read/write, unrestricted special block type SUBSEQUENT BYTES APU coefficient LL APU coefficient LR APU coefficient RL APU coefficient RR BIT 7 LL7 LR7 RL7 RR7 BIT 6 LL6 LR6 RL6 RR6 BIT 5 LL5 LR5 RL5 RR5 BIT 4 LL4 LR4 RL4 RR4 BIT 3 LL3 LR3 RL3 RR3 BIT 2 LL2 LR2 RL2 RR2 BIT 1 LL1 LR1 RL1 RR1 BIT 0 LL0 LR0 RL0 RR0
SAA2502
LOCAL ADDRESS 14H 15H 16H 17H
Table 43 Explanation of bits in Table 42 BIT LL7 to LL0 LR7 to LR0 RL7 to RL0 RR7 to RR0 range 0(1) to 255; see Fig.14 left channel in to right channel out attenuation index range 0 to 255(1); see Fig.14 right channel in to left channel out attenuation index range 0 to 255(1); see Fig.14 right channel in to right channel out attenuation index range 0(1) to 255; see Fig.14 Note 1. Default settings (settings value after a hard reset). The APU coefficient block type is a special one: * Block accesses may start at any individual coefficient (each has its own local address) * Block accesses may also extent past RR (the block access will wrap around to LL). DESCRIPTION left channel in to left channel out attenuation index
7.6.6.7
Interrupt control
Interrupt generation is controlled using two separate single byte local registers. Table 44 Interrupt event register: 1 byte (read-only, unrestricted type, local address = 1CH) BIT 7 undefined BIT 6 undefined BIT 5 undefined BIT 4 DST0U BIT 3 STOP BIT 2 CRCERR BIT 1 INSNC BIT 0 NOSNC
The separate bits of the interrupt event register indicate the occurrence of the events shown in Table 44
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ISO/MPEG Audio Source Decoder
Table 45 Explanation of bits in Table 44 BIT DST0U STOP CRCERR INSNC NOSNC rising edge of STOP input signal MPEG CRC check failed status bit INSYNC was set status bit INSYNC was cleared logic 0(1); no interrupt for this event logic 1; interrupt for this event Note 1. Default settings (settings value after a hard reset). Table 46 Interrupt masking register: 1 byte (write-only, unrestricted type, local address = 1DH) BIT 7 0 BIT 6 0 BIT 5 0 BIT 4 IMSK4 BIT 3 IMSK3 BIT 2 IMSK2 BIT 1 IMSK1 DESCRIPTION DST0 has been set (valid ancillary/PAD data, headers and error report)
SAA2502
BIT 0 IMSK0
The individual bits of the interrupt masking register (Table 46) may mask the interrupt events at the same bit location in the interrupt event register (Table 44): logic 0 (default setting, setting value after a hard reset); interrupt event is masked. logic 1; interrupt event is not masked. Masked interrupt are still flagged in the interrupt event register, they just do NOT have an effect on the INTRPT interrupt pin (thus polling of masked interrupts is possible).
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ISO/MPEG Audio Source Decoder
7.6.6.8 Frame headers
SAA2502
Information about input data, derived by the SAA2502 from the input data frame headers, may be read from the frame header items. Both the frame header bytes decoded from the input bit stream and the header bytes used for the actual decoding may be read. The decoded frame header item is valid independent of the value of status flag INSYNC. It shows, for example, the decoded headers while the SAA2500 is in the process of synchronizing. The used frame header item is only valid if status flag INSYNC is set. The used header bytes are derived by the SAA2502 from the decoded header bytes by filling in known header fields (e.g. those that have a fixed value) and overruling detected errors. Table 47 Decoded frame header: 3 bytes (read-only, restricted block type, local address = 21H) SUBSEQUENT BYTES Decoded header byte 1 Decoded header byte 2 Decoded header byte 3 Note 1. The EMPH1 and EMPH0 bits may only be used to monitor the current de-emphasis indication. Corresponding de-emphasis is performed automatically before outputting the baseband audio signal. Table 48 Used frame header: 3 bytes (read-only, restricted block type, local address = 22H) SUBSEQUENT BYTES Used header byte 1 Used header byte 2 Used header byte 3 Note 1. The EMPH1 and EMPH0 bits may only be used to monitor the current de-emphasis indication. Corresponding de-emphasis is performed automatically before outputting the baseband audio signal. Table 49 Explanation of bits in Tables 47 and 48 BIT SY3 to SY0 ID LAY1 and LAY0 NOPR BR3 to BR0 FS1 and FS0 MOD1 and MOD0 MODX1 and MODX0 COPR ORIG EMPH1 and EMPH0 last 4 bits of the synchronization word algorithm identification layer flag for CRC on header plus bit allocation plus scale factor select information bit rate index sample rate index mode mode extension copyright flag original or home copy flag audio de-emphasis indication DESCRIPTION BIT 7 1 BR3 MOD1 BIT 6 1 BR2 MOD0 BIT 5 1 BR1 MODX1 BIT 4 1 BR0 MODX0 BIT 3 ID FS1 COPR BIT 2 1 FS0 ORIG BIT 1 LAY0 BIT 0 NOPR BIT 7 SY3 BR3 MOD1 BIT 6 SY2 BR2 MOD0 BIT 5 SY1 BR1 MODX1 BIT 4 SY0 BR0 MODX0 BIT 3 ID FS1 COPR BIT 2 LAY1 FS0 ORIG BIT 1 LAY0 BIT 0 NOPR
undefined undefined EMPH1(1) EMPH0(1)
undefined undefined EMPH1(1) EMPH0(1)
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ISO/MPEG Audio Source Decoder
7.6.6.9 Error report
SAA2502
The validity of bit allocation plus scale factor select information and the result of the scale factor CRCs (only when scale factor CRCs are enabled) may be read from the error report register. The error report is only valid when status flag INSYNC is set. Table 50 Error report register: 1 byte (read-only, restricted type, local address = 24H) BIT 7 BALOK BIT 6 DECFM BIT 5 undefined BIT 4 undefined BIT 3 SF3OK BIT 2 SF2OK BIT 1 SF1OK BIT 0 SF0OK
Table 51 Explanation of bits in Table 50 BIT BALOK DESCRIPTION bit allocation and scale factor select information validity indication: logic 0; bit allocation or scale factor select information are incorrect or the CRC over header plus bit allocation plus scale factor select information has failed logic 1; bit allocation and scale factor select information are correct and CRC over header plus bit allocation plus scale factor select information is correct or not active DECFM frame skipping or frame decoding indication: logic 0; current input data frame is skipped, and the corresponding baseband audio output frame is muted due to input data errors or inconsistencies; audio frame synchronization is maintained logic 1; current frame is decoded normally SF3OK to SF0OK scale factor CRCs not enabled; bits are invalid scale factor CRCs enabled: logic 0; one or more scale factors have been concealed in sub-band block 0 to 3 logic 1; no scale factor concealment in sub-band block 0 to 3 (CRC check was OK) block 0; sub-bands 0 to 3 block 1; sub-bands 4 to 7 block 2; sub-bands 8 to 15 block 3; sub-bands 16 to 31
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ISO/MPEG Audio Source Decoder
7.6.6.10 Ancillary data and program associated data
SAA2502
With standard MPEG input data, the last 54 bytes of each frame, which may carry Ancillary Data (AD), are buffered by the SAA2502 to be read by the host. Subsequent ancillary data bytes are read in reversed order with respect to their order in the input data bit stream; the first item data byte is the last frame byte in the input bit stream. The ancillary data block of local registers is refilled for every frame. The host must either know or determine itself how many of the ancillary data bytes are valid per frame. The ancillary data block contains only valid data when status flag INSYNC is set. Table 52 Ancillary data: 54 bytes (read-only, restricted block type, local address = 25H) SUBSEQUENT BYTES AD byte 1 to byte 54 7 bit 7 6 bit 6 5 bit 5 4 bit 4 3 bit 3 2 bit 2 1 bit 1 0 bit 0
Similarly when scale factor CRCs are enabled, the Fixed Program Associated Data (FPAD) and extended Program Associated Data (XPAD) bytes contained in each frame may be read, with the 2 FPAD bytes first, followed by maximum 52 XPAD bytes. Subsequent FPAD and XPAD bytes are read in reversed order with respect to their order in the input data bit stream; the first item data byte is the last PAD byte in the input bit stream. The host must determine itself how many of the XPAD bytes are valid per frame by interpretation of the FPAD content. The PAD data block contains only valid data when status flag INSYNC is set. Table 53 XPAD plus FPAD: 54 bytes (read-only, restricted block type, local address = 25H) SUBSEQUENT BYTES FPAD bytes 1 and 2; XPAD byte 1 to byte 52 7 bit 7 6 bit 6 5 bit 5 4 bit 4 3 bit 3 2 bit 2 1 bit 1 0 bit 0
7.6.6.11
Continue block operation
Local address 00H is reserved for continuation of restricted type block operations. Whenever this local address is used, it will result in continuation of any restricted type block transfer at the point where it was interrupted (provided that no other restricted type SAA2502 transfer was carried out since).
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ISO/MPEG Audio Source Decoder
8 8.1 8.1.1 APPENDIX L3 interface specification INTRODUCTION
SAA2502
All slave devices in the system can be addressed using a 6 bit address. This allows for up to 63 different slave devices, as the all `0' address is reserved for special purposes. In operation 2 modes can be identified: 1. Addressing Mode (AM). During addressing mode a single byte is sent by the microcontroller. This byte consists of 2 Data Operation Mode (DOM) bits and 6 Operational Address (OA) bits. Each of the slave devices evaluates the operational address. Only the device that has been issued the same operational address will become active during the following data mode. The operation to be executed during the data mode is indicated by the two data operation mode bits. 2. Data Mode (DM). During data mode information is transferred between microcontroller and slave device. The transfer direction may be from microcontroller to slave (`write') or from slave to microcontroller (`read'). However, during one data mode the transfer direction can not change.
The main purpose of the interface definition is to define a protocol that allows for the transfer of control information and operational details between a microcontroller and a number of slave devices, at a rate that exceeds other common interfaces, but with a sufficient low complexity for application in consumer products. It should be clearly noted that the current interface definition is intended for use in a single apparatus, preferably restricted to a single printed circuit board. The interface requires 3 signal lines (apart from a return `ground') between the microcontroller and the slave devices (from this the name `L3' is derived). These 3-lines are common to all ICs connected to the bus: 1. L3MODE 2. L3DATA 3. L3CLK. L3MODE and L3CLK are always driven by the microcontroller, L3DATA is bidirectional: Table 54 The 3-lines common to all ICs; L3MODE, L3CLK and L3DATA SIGNAL MICROCONTROLLER SLAVE DEVICE input input input/output
8.1.1.1
Addressing mode
L3MODE(1) output L3CLK(2) L3DATA(3) Notes output output/input
In order to start an addressing mode the microcontroller will make the L3MODE line LOW. The L3CLK line is lowered 8 times during which the L3DATA line transfers 8 bits. The information is presented LSB first and remains stable during the LOW phase of the L3CLK signal. The addressing mode is ended by making the L3MODE line HIGH.
1. L3MODE is used for the identification of the operation mode. 2. L3CLK is the bit clock to which the information transfer will be synchronized. 3. L3DATA will carry the information to be transferred.
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ISO/MPEG Audio Source Decoder
SAA2502
handbook, halfpage
L3MODE
L3CLK
L3DATA
0
1
2
3
4
5
6
7
MGB505
The meaning of the bits on L3DATA. Bit 0 and bit 1; these are the Data Operation Mode (DOM) bits that indicate the nature of the following data transfer. The preferred allocations are given in Table 55. Bit 2 to bit 7; these bits act as 6 bit operational IC address, with bit 7 as MSB and bit 2 as LSB.
Fig.21 Addressing mode.
Table 55 Preferred allocations DOM1 0 0 1 1 DOM0 0 1 0 1 FUNCTION data from microcontroller to SAA2500 data from SAA2500 to microcontroller control from microcontroller to SAA2500 status from SAA2500 to microcontroller REMARKS general purpose data transfer general purpose data transfer register selection for data transfer short device status message
8.1.1.2
Data mode
8.1.1.3
Halt mode
In the data mode the microcontroller sends or receives information to or from the selected device. During data transfer the L3MODE line is HIGH. The L3CLK line is lowered 8 times during which the L3DATA line carries 8 bits. The information is presented LSB first and remains stable during the LOW phase of the L3CLK signal. The basic data transfer unit is an 8-bit byte. No other basic data transfer unit is allowed.
In between transfer units the L3MODE line will be driven LOW by the microcontroller to indicate the completion of a unit transfer. This is called `Halt Mode' (HM). During halt mode the L3CLK line remains HIGH (to distinguish it from an addressing mode).
handbook, halfpage
L3MODE
L3CLK
L3DATA
0
1
2
3
4
5
6
7
MGB504
Fig.22 Data transfer mode.
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Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
8.1.2 EXAMPLE OF A DATA TRANSFER
SAA2502
handbook, full pagewidth
L3 MODE
L3CLK
L3DATA
address
data byte1
data byte2
data byte3
data byte4
address
MGE485
Fig.23 Example of transfer of 4 bytes.
A data transfer starts when the microcontroller sends an address on the bus. All ICs will evaluate this address, but only the IC addressed will be an active partner for the microcontroller in the following data transfer mode. During the data transfer mode bytes will be sent from or to the microcontroller. The L3MODE line is made LOW (`halt mode') in between byte transfers. Only bytes should be used as basic data transfer units.
After the data transfer the microcontroller does not need to send a new address until a new data transfer is necessary. 8.1.3 TIMING REQUIREMENTS
These are requirements for the slave devices designed in accordance with the `L3' interface definitions.
8.1.3.1
Addressing mode
handbook, full pagewidth
t d1 L3MODE t cL t cH
t h2
L3CLK
L3DATA t su t h1
MGB507
Fig.24 Timing (addressing mode).
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Preliminary specification
ISO/MPEG Audio Source Decoder
8.1.3.2 Data transfer
SAA2502
andbook, full pagewidth
t d1 L3MODE t cL L3CLK t su t h1 t cH
t h2
L3DATA microcontroller to IC L3DATA IC to microcontroller t d2 t d3
t h3
t d4
t d5
MGB508
Fig.25 Timing (data transfer).
8.1.3.3
Halt mode
handbook, full pagewidth
tL L3MODE t h2 L3CLK td5 L3DATA IC to microcontroller
MGB509
t d1
t d2
Fig.26 Timing (halt mode).
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ISO/MPEG Audio Source Decoder
Table 56 Requirements for timing; note 1 SYMBOL PARAMETER MIN. - - - - - - - MAX.
SAA2502
UNIT
Microcontroller to slave device; note 2 tcL tcH td1 th1 th2 tsu tL td2 td3 td4 td5 th3 Notes 1. L3DATA output timing is given with 0 pF external load (derating of maximum delay = 0.5 ns/pF). Maximum external L3DATA load = 50 pF. 2. T = 4 x MCLKIN cycle time if MCLK24 = logic 1; T = 2 x MCLKIN cycle time if MCLK24 = logic 0. 8.1.4 TIMING L3CLK LOW time L3CLK HIGH time L3MODE set-up time before first L3CLK LOW L3DATA hold time after L3CLK HIGH L3MODE hold time after last L3CLK HIGH L3DATA set-up time before L3CLK HIGH L3MODE LOW time T + 10 T + 10 10 10 15 T + 10 T + 10 ns ns ns ns ns ns ns
Slave device to microcontroller; note 2 L3MODE HIGH to L3DATA enabled time L3MODE HIGH to L3DATA stable time L3CLK HIGH to L3DATA stable time L3MODE LOW to L3DATA disabled time L3DATA hold time after L3CLK HIGH 0 - - 0 T 20 20 2T + 30 20 - ns ns ns ns ns
8.1.4.1
General ancillary data
If the last part of an audio frame is not occupied by encoded sub-band samples, it may be used to transfer any other data. Definition of size, format and meaning of this so called ancillary data is completely up to the application (there are no MPEG requirements). Non-byte aligned layer I coded input audio frames should however preferably not (always) end with a logic 1 valued bit. In practice there are two common ways to define the size of ancillary data: * The number of ancillary data bytes per frame is fixed and known by the application. * There is a fixed minimum size of the ancillary data block (usually this size is small; one or two bytes). The fixed part of the block then contains an indication of the actual size of the ancillary data block. If room for ancillary data is present the content will be stored to be read by the microcontroller (up to a maximum of 54 bytes).
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ISO/MPEG Audio Source Decoder
8.1.4.2 Ancillary data containing scale factor CRCs
SAA2502
If scale factor CRC protection is enabled, the required CRC values for each audio frame are carried among the ancillary data of the previous frame. This approach ensures MPEG compatibility for encoded streams with scale factor protection. The SAA2502 assumes the next ancillary data format when scale factor CRC protection is enabled: * The last 2 bytes of each audio frame carry the minimum ancillary data. These two bytes are called FPAD (fixed program associated data) bytes. Definition of the content of FPAD is up to the application but should contain information on the length of the remainder of the ancillary data if that length is variable. FPAD bytes are stored to be read by the microcontroller. * The byte before the FPAD bytes is called CRC0 and contains the scale factor CRC for sub-bands 0 to 3. * The byte before CRC0 is called CRC1 and contains the scale factor CRC for sub-bands 4 to 7. * An optional byte CRC2 may precede CRC1. It contains the scale factor CRC for sub-bands 8 to 15 and is present only for sub-band limits greater than 8. * There may be an optional byte CRC3 before CRC2. It contains the scale factor CRC for sub-bands 16 to 31 and will be present only for sub-band limits greater than 16. * Before the sub-band CRCs more ancillary data may be present. This extra ancillary data is called XPAD (extended program associated data). If XPAD is present it will be stored to be read by the microcontroller (up to a maximum of 52 bytes).
handbook, full pagewidth XPAD
52 optional
--optional
XPAD 1 optional
CRC 3 optional
CRC 2 optional
CRC 1
CRC 0
FPAD 2
FPAD 1 start of frame n + 1
MGE486
end of frame n
Fig.27 Ancillary data containing scale factor CRCs.
8.1.4.3
Boundary scan test provision
The SAA2502 contains a 5-pin interface for Boundary Scan Test (BST): Table 57 Boundary scan test SIGNAL TDI TDO TMS TCK TRST DIRECTION input output input input input FUNCTION boundary scan test data input boundary scan test data output boundary scan test mode select boundary scan test clock boundary scan test reset
In normal use TRST must be LOW, TCK must be LOW or HIGH while TDI and TMS must be HIGH or not connected. Otherwise when any of these pins is used in a way not designed correctly for boundary scan test purposes in the application, damaging of the SAA2502 and/or the components surrounding it may occur.
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ISO/MPEG Audio Source Decoder
Table 58 Boundary scan controller instructions OPCODE Binary 000 Binary 001 Binary 010 Binary 011 Binary 100 Binary 101 Binary 110 Binary 111 INSTRUCTION ExTest IDcode sample clamp InTest STCtest undefined bypass
SAA2502
Table 59 Boundary scan register definition NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Notes 1. LOW or HIGH control of 2 state output. 2. LOW or HIGH control of 3 state output. 3. LOW or HIGH impedance control of 3 state output. 4. LOW or HIGH impedance control of open drain output. PORT FSCLK SCK SD WS SPDIF TC0 TC1 FSCLKIN REFCLK X22IN MCLK24 MCLKIN PHDIF PHDIF INT RESET STOP CDRQ CDEF CDCL CDCL CDCL CD CDSY CDVAL CCLK CDATA CDATA CDATA CMODE FUNCTION output 2; note 1 output 2; note 1 output 2; note 1 output 2; note 1 output 2; note 1 input input input input input input input output 3; note 2 control; note 3 open drain; note 4 input input output 2; note 1 input input output 3; note 2 control; note 3 input input input input input open drain; note 4 control; note 3 input
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Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
8.1.4.4 Factory test scan chain provision
SAA2502
Table 60 Signals provided for factory test scan chain control SIGNAL TC0 TC1 DIRECTION input input FUNCTION factory test scan chain control 0 factory test scan chain control 1
In normal use factory test scan chain control pins must be not connected or kept LOW. If any of these pins are pulled HIGH in the application, damage to the SAA2502 and/or the surrounding components may occur.
8.1.4.5
Provision to read internal status
The following internal status information is made available for reading. It provides designers additional information on status and/or progress of internal processes. This information has no meaning for the application. Table 61 Transcoder program counter register: 1 byte (read-only, unrestricted type, local address = 10H) BIT 7 tPC11 BIT 6 tPC9 BIT 5 tPC8 BIT 4 tPC7 BIT 3 tPC6 BIT 2 tPC5 BIT 1 tPC4 BIT 0 tPC3
Table 62 Decoder program counter register: 1 byte (read-only, unrestricted type, local address = 11H) BIT 7 tPC7 BIT 6 tPC6 BIT 5 tPC5 BIT 4 tPC4 BIT 3 tPC3 BIT 2 tPC2 BIT 1 tPC1 BIT 0 tPC0
Table 63 Transcoder flag register: 1 byte (read-only, unrestricted type, local address = 12H) BIT 7 Undefined BIT 6 tNSYNC BIT 5 tORENB BIT 4 tIRENB BIT 3 tCRC16 BIT 2 tCRCF BIT 1 tERRF BIT 0 tSKF
Table 64 Transcoder and decoder branch conditions register: 1 byte (read-only, unrestricted type, local address = 13H) BIT 7 dOFUL BIT 6 dIRDY BIT 5 dOREQ BIT 4 tIEMT BIT 3 tOREQ BIT 2 tUPREQ BIT 1 tIREQ BIT 0 tPOR
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ISO/MPEG Audio Source Decoder
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD Vi IDD ISS II IO Ptot Tstg Tamb Ves input voltage supply current supply current input current output current total power dissipation storage temperature operating ambient temperature electrostatic handling note 2 note 3 Notes 1. Input voltage should not exceed 6.5 V unless otherwise specified. 2. Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. 3. Equivalent to discharging a 200 pF capacitor through a 0 series resistor. PARAMETER supply voltage note 1 CONDITIONS MIN. -0.5 -0.5 - - -10 -20 - -65 -40 -2000 -200
SAA2502
MAX. +6.5 VDD + 0.5 100 100 +10 +20 163 +150 +85 +2000 +200 V V
UNIT
mA mA mA mA mW C C V V
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ISO/MPEG Audio Source Decoder
10 DC CHARACTERISTICS VDD = 4.5 to 5.5 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Inputs VIH VIL VIH VIL VtLH VtHL Vhys II Rpull Outputs VOH VOL ILO Notes 1. Only applies to pin 25 (FSCLKIN). 2. Boundary scan test inputs. 3. All inputs except for TC0, TC1, FSCLKIN, MCLKIN, X22IN, REFP and REFN. 4. DAC outputs IOH = 2 mA. Typical DAC output impedance = 125 . HIGH level output voltage LOW level output voltage leakage current of a disabled output note 4 note 4 VDD - 0.5 - - - - - - HIGH level input voltage (CMOS) LOW level input voltage (CMOS) HIGH level input voltage (TTL) LOW level input voltage (TTL) rising edge threshold voltage (CMOS hysteresis) falling edge threshold voltage (CMOS hysteresis) hysteresis voltage (CMOS hysteresis) input current (all input types) pull-up or pull-down resistance note 1 note 1 note 2 note 2 note 3 note 3 0.7VDD - 2 - - 0.2VDD - -5 14 - - - - - - 0.3VDD - - - PARAMETER CONDITIONS MIN. TYP.
SAA2502
MAX.
UNIT
V V V V V V V A k
0.3VDD - 0.8 0.8VDD - - +5 140
V V A
0.5 5
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ISO/MPEG Audio Source Decoder
11 AC CHARACTERISTICS VDD = 4.5 to 5.5 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Clock inputs MCLKIN Tcy tH tL X22IN Tcy tH tL FSCLKIN Tcy tH tL REFCLK Tcy tH tL CDCL Tcy tH tL cycle time HIGH time LOW time note 1 note 1 note 1 8xT T + 10 T + 10 - - - - - - cycle time HIGH time LOW time 33 12 12 - - - - - - cycle time HIGH time LOW time 54 12 12 - - - - - - cycle time HIGH time LOW time 44 12 12 - - - - - - cycle time HIGH time LOW time 40 12 12 - - - - - - PARAMETER CONDITIONS MIN. TYP.
SAA2502
MAX.
UNIT
ns ns ns
ns ns ns
ns ns ns
ns ns ns
ns ns ns
Clock outputs FSCLK Tcy tH tL CDCL Tcy tH tL SCK Tcy tH tL cycle time HIGH time LOW time note 2 note 2 note 2 2xS S - 10 S - 10 - - - - - - ns ns ns cycle time HIGH time LOW time note 1 note 1 note 1 8xT - - - - ns ns ns 4 x T - 10 - 4 x T - 10 - cycle time HIGH time LOW time 54 10 10 - - - - - - ns ns ns
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ISO/MPEG Audio Source Decoder
SAA2502
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Data inputs: CD, CDEF, CDSY, CDVAL, TDI and TMS tsu set-up time CD, CDEF, CDSY and CDVAL TDI and TMS th tsu th tH hold time CD, CDEF, CDSY and CDVAL set-up time CD, CDEF, CDSY and CDVAL hold time CD, CDEF, CDSY and CDVAL TDI and TMS HIGH time CDCL clock; note 3 CDCL clock; notes 1 and 4 CDCL clock; note 4 CDCL clock; note 3 42 50 0 T + 10 10 50 - - - - - - - - - - - - ns ns ns ns ns ns
Data outputs CDRQ tPD SD AND WS tPD TDO tPD THD + N DR cs Notes 1. T = 4 x MCLKIN cycle time if MCLK24 = logic 1; T = 2 x MCLKIN cycle time if MCLK24 = logic 0. 2. S is the audio sample time divided by 128. a) Maximum external clock output load = 25 pF. 3. When CDCL is output (input master mode or buffer controlled mode). 4. When CDCL is input (input slave mode). 5. A negative value of tPD means that the output changes before the falling edge of the clock. a) Propagation delay times are given with an external load of 0 pF. b) Maximum external output load = 50 pF. c) Output load derating of maximum propagation delay time is 0.5 ns per pF. 6. Sample frequency = 44.1 kHz. propagation delay time TDO TCK clock; note 5 0 - - - - -75 75 -92 100 - - - ns propagation delay time SD and WS SCK clock; note 5 -22 - +10 ns propagation delay time CDRQ CDCL clock; note 5 -22 - +10 ns
Analog output performance; note 6 total harmonic distortion plus noise dynamic range channel separation dB dB dB
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ISO/MPEG Audio Source Decoder
SAA2502
handbook, full pagewidth
Tcy tH tL
CLOCK
INPUT
,, ,, ,,
tsu
,,,,,,, ,,, ,,,,,,, ,,, ,,,,,,, ,,,
th tsu th tPD
MGE487
OUTPUT
Fig.28 Timing diagram.
11.1
Host interface: CDATA, CCLK and CMODE
For L3 mode host interface timing information is detailed in the Section 8.1. The I2C-bus mode host interface timing is master clock dependent, adherence to this specification is only guaranteed for the maximum MCLKIN frequency. If MCLKIN frequency is below maximum in principle all timing figures should be increased proportionally. Table 65 Supported REFCLK frequencies REFCLK (kHz) 6 25.6 51.2 76.8 102 121.6 147.2 172.8 198.4 224 264 304 6.4 28.8 54 78 102.4 124.8 150 174 200 228 268.8 307.2 8 30 56 80 104 126 152 176 201.6 230.4 270 312 9.6 32 57.6 83.2 105.6 128 153.6 179.2 204 232 272 320 12 36 60 84 108 132 156 180 204.8 240 276 324 12.8 38.4 64 86.4 108.8 134.4 160 182.4 208 248 278.4 326.4 16 40 66 88 112 136 162 184 210 249.6 280 330 18 42 67.2 89.6 114 138 163.2 185.6 211.2 252 288 336 19.2 44.8 70.4 90 115.2 140.8 166.4 186 216 256 297.6 345.6 24 48 72 96 120 144 168 192 220.8 259.2 300 348
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ISO/MPEG Audio Source Decoder
352 416 464 537.6 608 696 810 920 1050 1248 1400 1650 1950 2240 2560 2850 3300 3800 4400 5040 5760 6750 7800 9120 10560 12400 13600 15600 18000 20800 23250 27600 360 420 480 540 614.4 704 816 928 1056 1260 1440 1680 2000 2250 2592 2880 3360 3840 4480 5100 5800 6800 8000 9200 10800 12480 13800 15750 18400 21000 24000 28000 364.8 422.4 496 544 624 720 832 930 1080 1280 1488 1728 2016 2280 2600 2976 3400 3900 4500 5120 6000 6900 8100 9300 11000 12600 13920 16000 18600 21600 24800 28500 368 432 499.2 552 630 736 840 960 1104 1296 1500 1740 2040 2304 2640 3000 3450 4000 4560 5200 6200 6960 8160 9600 11040 12750 14000 16200 18750 21750 25000 28800 372 440 504 556.8 640 744 864 992 1120 1320 1520 1760 2080 2320 2688 3040 3480 4050 4600 5250 6240 7000 8250 9750 11200 12800 14250 16500 19000 22000 25200 29000 384 441.6 510 560 648 750 870 1000 1140 1344 1536 1800 2100 2400 2700 3072 3520 4080 4640 5280 6300 7200 8400 10000 11250 12960 14400 16800 19200 22400 25500 30000 390 448 512 570 660 760 880 1008 1152 1350 1560 1824 2112 2480 2720 3120 3600 4160 4650 5400 6400 7440 8640 10080 11400 13000 14880 17000 19500 22500 25600 - 400 450 518.4 576 672 768 896 1020 1160 1360 1600 1840 2160 2496 2760 3150 3680 4200 4800 5520 6480 7500 8700 10200 11520 13200 15000 17250 20000 22800 26000 - 403.2 456 520 595.2 680 780 900 1024 1200 1380 1620 1860 2200 2520 2784 3200 3720 4320 4960 5600 6600 7600 8800
SAA2502
408 460.8 528 600 690 800 912 1040 1240 1392 1632 1920 2208 2550 2800 3240 3750 4350 5000 5700 6720 7680 9000 10500 12000 13500 15360 17600 20400 23200 27000 -
10400 11600 13440 15200 17400 20250 23000 26400 -
1997 Nov 17
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k, full pagewidth
RESET
INT
CMODE
CDATA
CCLK
SPDIF
TRST
WS
SD
SCK
FSCLK
TDI
TCK
PHDIF
X22IN
GND2
VDD2
X22OUT
FSCLKIN
MCLK24
MLCKOUT
MLCKIN
1997 Nov 17
I2C-bus clock SPDIF O/P VA1 R16 1 44 43 42 41 TDO R1 10 k VA1 10 k C3 390 pF R4 10 k 3 2 4 U2 TDA1308T 5 6 100 F +2.5 V R12 11 k C10 220 pF C11 220 pF R13 C13 100 F C14 100 nF 11 k
MGG817
reset
I2C-bus data
Philips Semiconductors
+5 V
11 7 VDD3 TC1 GND3 220 pF R6 R2 11 k C1 10 nF 4.7 H C5 4.7 C2 100 F R15 L1 6 5 4 3 2
10
9
8
4.7 +5 V
12 APPLICATION INFORMATION
STOP
12
CDRQ
13
data clock
CDCL
14
data
CD
15
+5 V 40
GND1 TC0 LFTPOS LFTNEG REFP REFN 36 35 34 27 R10 +5 V 10 k 10 k 28 29 30 31 32 33 RGTPOS 10 k RGTNEG R8 R9 R5 11 k C4 220 pF 8 1 10 k R3
U1 SAA2502
39 38 37
16
CDEF
17
ISO/MPEG Audio Source Decoder
VDD1
18
C6 10 nF
C7 100 F
sync signal
CDSY
19
58
10 k C9 390 pF R11
CDVAL
20
C8 100 F
left
TMS
21
REFCLK
22
analog 7 C12 right
23
24
25
26
12.228 MHz
R14 10 k
R7 10 k
Preliminary specification
SAA2502
Fig.29 Application circuit for ADR.
Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
13 PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SAA2502
SOT307-2
c
y X
A 33 34 23 22 ZE
e E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vMA 12 detail X A A2 (A 3) Lp L
A1
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
1997 Nov 17
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ISO/MPEG Audio Source Decoder
14 SOLDERING 14.1 Introduction 14.3 Wave soldering
SAA2502
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 14.2 Reflow soldering
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 Repairing soldered joints
Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C.
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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ISO/MPEG Audio Source Decoder
15 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA2502
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 16 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
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ISO/MPEG Audio Source Decoder
NOTES
SAA2502
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Preliminary specification
ISO/MPEG Audio Source Decoder
NOTES
SAA2502
1997 Nov 17
63
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA56
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547027/00/02/pp64
Date of release: 1997 Nov 17
Document order number:
9397 750 03068

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